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posted by Fnord666 on Monday May 14 2018, @10:25PM   Printer-friendly
from the hot-tech dept.

The Taiwan Semiconductor Manufacturing Company (TSMC) has revealed a manufacturing technique (called wafer-on-wafer or WoW) that could allow CPUs and GPUs to take their first step towards vertical scaling:

Instead of one wafer per chip, future GPUs may include two or more wafers stacked vertically, which would double the performance without the need to develop new horizontal designs every 2 years. A dual wafer setup, for example, would be achieved by flipping the upper wafer over the lower one, binding both via a flip-chip package. Thus, future GPUs could include multiple wafers in one die and the operating system could detect it as a multi-processor graphics card, eliminating the need for SLI setups.

One shortcoming for this technology would be its lower manufacturing yields for sizes lower than 16 nm. If one of the stacked wafers does not pass the QA, the entire stack is discarded, leading to low yields and poor cost effectiveness. TSMC is currently working to improve this technology so that sub-12 nm processes could equally benefit from it.

Not discussed is how to deal with the heat generated in such a stack.

See also: Here's why Intel and AMD's 7nm CPU revolution is so important to the future of PCs


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  • (Score: 2) by ese002 on Tuesday May 15 2018, @12:43AM (2 children)

    by ese002 (5306) on Tuesday May 15 2018, @12:43AM (#679849)

    Moore's law is driven by the expectation that wafer cost is more or less constant but newer processes allow more transistors to be packed on each wafer for "free".

    If, instead of waiting for the process to double in density, you stack two wafers, you have doubled your manufacturing costs and that is before the yield hit is factored in. So cost is probably at least 3x for less than 2x performance and area.

    The statement about not having to incur design costs are is bogus too. The interconnect has between the dies has to be designed too, along with the TSV's to reach the package pins. That's a significant cost in area and complexity so you probably won't do that for the first generation single-level chip. So, you need to design anew anyway.

    So, what we have here is a technology for the most demanding consumers who want the highest performance available and are willing to pay for it. I don't see much application for the mainstream.

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  • (Score: 2) by takyon on Tuesday May 15 2018, @03:47AM (1 child)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Tuesday May 15 2018, @03:47AM (#679929) Journal

    It's possible that two stacked wafers is somewhat cheaper than two wafers. Like how 64-layer NAND is not 64 times more expensive than 1/64 amount of planar NAND. In that case, there will be eager customers - probably not home users though.

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    • (Score: 2) by ese002 on Tuesday May 15 2018, @05:33PM

      by ese002 (5306) on Tuesday May 15 2018, @05:33PM (#680103)

      It's possible that two stacked wafers is somewhat cheaper than two wafers. Like how 64-layer NAND is not 64 times more expensive than 1/64 amount of planar NAND. In that case, there will be eager customers - probably not home users though.

      3D NAND is a monolith process. They don't fabricate 64 wafers and then stack them. They deposit 64 layers onto a single substrate (a relatively cheap operation) and then do a single exposure and etch through all 64 layers. It is really cool tech but only applicable to rigidly structured memory designs.