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Spotted over on Phoronix:
While free software/hardware advocates have been ecstatic about the RISC-V open-source, royalty-free processor architecture, hardware so far hasn't been as open as desired.
While this processor ISA is entirely open and living up to its merits, it turns out the RISC-V implementations so far haven't been quite as open as one would have thought. A Phoronix reader pointed out to us some remarks by developers on the main RISC-V development board out so far, the SiFive HiFive Unleashed
Ron Minnich who has run the Coreboot project for more than the past decade and spearheads the effort of getting Coreboot on new Chrome OS devices at Google, commented on the Unleashed development board this weekend:
All this said, note that the HiFive is no more open, today, than your average ARM SOC; and it is much less open than, e.g., Power. I realize there was a lot of hope in the early days that RISC-V implied "openness" but as we can see that is not so. There's blobs in HiFive.
Open instruction sets do not necessarily result in open implementations. An open implementation of RISC-V will require a commitment on the part of a company to opening it up at all levels, not just the instruction set.
The issue stems from the use of third party IP used to complete the SoC as Risc-V is an instruction set, not a physical hardware design. The actual silicon of the CPU must be designed in order to implement the instruction set as actual hardware and glue logic to tie the CPU to other hardware like memory and bus controllers. In the case, the HiFive Unleashed features a DRAM controller from Cadence which uses a proprietary binary blob to initialize the DRAM controller. This makes open firmware implementations legally difficult.
(Score: 2, Disagree) by qzm on Tuesday June 26 2018, @05:23AM (2 children)
Talk about a clickbaiting article.
RISC-V is open, which means anyone is free to implement it, THAT is the point of it.
What is being complained about here has NOTHING WHAT SO EVER tyo do with the openness of RISC-V, and smells more of someone trying to create some political pressure to get what they want.
Their issue is actually with the system peripherals implemented on a SOC (system on a chip) next to the core, and THOSE are not RISC-V.
Now, that is a common problem, that GPUs, memory interfaces, external busses, etc may not be as open as the CPU next to them, but ffs, that has NOTHING to do with RISC-V being open.
It is like claiming the Linux kernel is not open because a particular distribution contains some binaries without source (not even in the kernel)..
Still, decent journalism, decent technical reporting, and critical thinking all seems to have sailed past quite some time ago, so why not.
(Score: 5, Insightful) by ledow on Tuesday June 26 2018, @07:31AM
These people are piggy-backing on an "open" project and then closing it.
This is not "RISC-V is closed". This is "these people are closing it for their own purposes / laziness", and people need to be aware of that.
If something appears in a shop with RISC-V on it, and people have been taught to associate RISC-V with "open", that's not going to end well when the binary blob contains a root-level compromise that nobody can see / fix until it's too late, is it?
Also, there's no point having an open architecture if even a handful of the actual, physical examples you can realistically buy are not open. It just defeats the entire point.
That's not to say they've done anything illegal, it just leaves a sour taste. They are taking and not giving back. And there are other DRAM controllers they could have used, and other ways they could have implemented them.
Fact is that the RISC-V "open" architecture in any OS now has to carry around a bunch of closed-source binary blobs if you want it to boot on the machines that you can buy implementing that architecture. So... what's different between that and a Raspberry Pi, or an Intel, or anything else?
If it were the graphics core, or the networking chip, or something completely secondary to the operation of the machine, you could avoid it, disable it, substitute it, etc. But it's the DRAM controller. The machine won't even turn on for more than a second without initialising that.
It might be one model, one business decision, etc. but if that creep is allowed to continue then RISC-V as a practical, implemented architecture (i.e. the bits people can actually BUY) will lose its main advantage and be no different to anything else currently on the market. That's a lot of hard work down the drain.
Combat it now, and you may yet still keep RISC-V and its implementations clean, by putting pressure on the company to licence and open that blob, or replace it with something equivalent.
(Score: 4, Informative) by Anonymous Coward on Tuesday June 26 2018, @07:53AM
The Phoronix title:
The Soylent title:
Which of these are clickbait? Which of them claims RISC-V is not open? Both refer to current hardware implementations. Please do not invent clickbait in your head, there is enough to go around.