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TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019
Last week, TSMC made two important announcements concerning its progress with extreme ultraviolet lithography (EUVL). First up, the company has successfully taped out its first customer chip using its second-generation 7 nm process technology, which incorporates limited EUVL usage. Secondly, TSMC disclosed plans to start risk production of 5 nm devices in April.
TSMC initiated high-volume manufacturing of chips using its first generation 7 nm fabrication process (CLN7FF, N7) in April. N7 is based around deep ultraviolet (DUV) lithography with ArF excimer lasers. By contrast, TSMC's second-generation 7 nm manufacturing technology (CLN7FF+, N7+) will use extreme ultraviolet lithography for four non-critical layers, mostly in a bid to speed up production and learn how to use ASML's Twinscan NXE step-and-scan systems for HVM. Factual information on the improvements from N7 to N7+ are rather limited: the new tech will offer a 20% higher transistor density (because of tighter metal pitch) and ~8% lower power consumption at the same complexity and frequency (between 6% and 12% to be more precise).
[...] After N7+ comes TSMC's first-generation 5 nm (CLN5FF, N5) process, which will use EUV on up to 14 layers. This will enable tangible improvements in terms of density, but will require TSMC to extensively use EUV equipment. When compared to TSMC's N7, N5 technology will enable TSMC's customers to shrink area of their designs by ~45% (i.e. transistor density of N5 is ~1.8x higher than that of N7), increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction[sic] (at the same frequency and complexity).
TSMC will be ready to start risk production of chips using its N5 tech in April, 2019. Keeping in mind that it typically takes foundries and their customers about a year to get from risk production to HVM, it seems like TSMC is on-track for mass production of 5 nm chips in Q2 2020, right in time to address smartphones due in the second half of 2020.
Tape-out. Risk production = early production.
Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
Related: TSMC to Build 7nm Process Test Chips in Q1 2018
"3nm" Test Chip Taped Out by Imec and Cadence
TSMC Will Make AMD's "7nm" Epyc Server CPUs
GlobalFoundries Abandons "7nm LP" Node, TSMC and Samsung to Pick Up the Slack
(Score: 2) by VLM on Wednesday October 10 2018, @10:55PM (1 child)
It means something VERY hand wavy like the radius of a one bit cell in a SDRAM which is a weird way to spec a CPU because CPUs are not very dense.
If I did the math in my head correctly (quite likely wrong) a "10 nm process" Apple A11 has 4E9 transistors on 88 sq mm which is something like 88e-3 ** 0.5 / 4e9 ** 0.5 * 1e9 results in the average transistor having a cell about 4690 nm to live in. Which seems wrong somehow, but it is after all a CPU even if most of the transistors are on chip cache ram.
Anyway dram is tightly packed and if you had an old fashioned 45 nm process that gets the figure of merit F. Then the wordline pitch will be 2F and bitline pitch 2F aka 90 nm and the cell area is 6 F squared and all that. There are immense spreadsheets calculating everything off "F". Thats capacitor over bitline where the caps are double sided vertical tubesies with something like 4 interconnect layers (or do you need five? I'm tired). Theres a boring as hell 100+ page PDF of a power point that I have somewhere from some memory producer but they all have stuff like this if you google for it. The point is for any "half pitch feature number" F there are plug and chug spreadsheets to make ridiculously accurate estimates for how much space a SDRAM chip of capacity X would require hence how many you get from a single slice of expensive silicon and also you can predict failure rates based on size and heat and all kinds of BS. They even model how far the wire bonder has to move across the die in their spreadsheets, supposedly..
I don't know if there's anything quite like this in FPGAs (at least in public) where you can take the funky F value and turn it into an Alterra ALM element will be 85.323F in width and 10F in length or each MLAB memory-logic clump (I think there's a more professional term than clump, but whatevs) is 259F in width or similar enough. It works for memory, it doesn't work for CPUs, it MIGHT work for FPGAs.
You are correct its much like seconds of specific impulse for a rocket motor where you can predict and model fairly accurately which engine is more gooder, but it doesn't mean very much. A second of specific impulse is something like the rocket could levitate fuel for that many seconds if it didn't burn fuel while levitating in a non-calculus sorta way, kinda. Or if you wanted to levitate a bucket of fuel (in the sense of total mass, including oxidizer) then it would burn 1/Isp of the fuel to levitate every second. Levitate as in apply 1G. The official definition is a figure of merit that falls out as seconds.
In summary it means very little for a CPU but for memory bean counters they can drop F into a spreadsheet and forecast tiny details into infinity. CPU guys not so much because CPUs are internally so random and confusing. Other guys (FPGAs and stuff) in between usefulness.
(Score: 0) by Anonymous Coward on Thursday October 11 2018, @12:02PM
Isp on a rocket motor is much simpler and more useful than that. It is basically how many pounds of thrust you get for each pound of fuel you burn per second.
Isp = Thrust (pounds) /Fuel consumption (pounds/sec)
The reason pounds are still used is that they cancel out nicely*, leaving you with a single number that is a pretty good metric for how good your motor is.
Another way to look at it is one pound of fuel will provide one pound of thrust for Isp seconds.
*they shouldn't really, one is Force, the other should be Mass, but if you weigh your fuel on the ground it works.