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posted by CoolHand on Monday November 05 2018, @10:04PM   Printer-friendly
from the revived-competition dept.

Intel announces Cascade Lake Xeons: 48 cores and 12-channel memory per socket

Intel has announced the next family of Xeon processors that it plans to ship in the first half of next year. The new parts represent a substantial upgrade over current Xeon chips, with up to 48 cores and 12 DDR4 memory channels per socket, supporting up to two sockets.

These processors will likely be the top-end Cascade Lake processors; Intel is labelling them "Cascade Lake Advanced Performance," with a higher level of performance than the Xeon Scalable Processors (SP) below them. The current Xeon SP chips use a monolithic die, with up to 28 cores and 56 threads. Cascade Lake AP will instead be a multi-chip processor with multiple dies contained with in a single package. AMD is using a similar approach for its comparable products; the Epyc processors use four dies in each package, with each die having 8 cores.

The switch to a multi-chip design is likely driven by necessity: as the dies become bigger and bigger it becomes more and more likely that they'll contain a defect. Using several smaller dies helps avoid these defects. Because Intel's 10nm manufacturing process isn't yet good enough for mass market production, the new Xeons will continue to use a version of the company's 14nm process. Intel hasn't yet revealed what the topology within each package will be, so the exact distribution of those cores and memory channels between chips is as yet unknown. The enormous number of memory channels will demand an enormous socket, currently believed to be a 5903 pin connector.

Intel also announced tinier 4-6 core E-2100 Xeons with ECC memory support.

Meanwhile, AMD is holding a New Horizon event on Nov. 6, where it is expected to announce 64-core Epyc processors.

Related: AMD Epyc 7000-Series Launched With Up to 32 Cores
AVX-512: A "Hidden Gem"?
Intel's Skylake-SP vs AMD's Epyc
Intel Teases 28 Core Chip, AMD Announces Threadripper 2 With Up to 32 Cores
TSMC Will Make AMD's "7nm" Epyc Server CPUs
Intel Announces 9th Generation Desktop Processors, Including a Mainstream 8-Core CPU


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  • (Score: 0) by Anonymous Coward on Monday November 05 2018, @10:49PM (3 children)

    by Anonymous Coward on Monday November 05 2018, @10:49PM (#758245)

    Imagine 50 roads between two cities with a speed limit of 60 mph vs 5000 roads with a speed limit of 30 mph.

  • (Score: 0) by Anonymous Coward on Monday November 05 2018, @10:52PM

    by Anonymous Coward on Monday November 05 2018, @10:52PM (#758247)

    The 50 roads need to be 4 lanes wide while the 5000 roads are 2 lanes wide.

  • (Score: 2) by shortscreen on Tuesday November 06 2018, @09:30AM (1 child)

    by shortscreen (2252) on Tuesday November 06 2018, @09:30AM (#758429) Journal

    If there are 5000 roads, are there also 5000 cops? Or maybe there is a higher "undocumented" speed limit.

    • (Score: 0) by Anonymous Coward on Tuesday November 06 2018, @02:25PM

      by Anonymous Coward on Tuesday November 06 2018, @02:25PM (#758491)

      The roads will crumble if you drive over the speed limit without proper preperation.