AMD has announced the next generation of its Epyc server processors, with up to 64 cores (128 threads) each. Instead of an 8-core "core complex" (CCX), AMD's 64-core chips will feature 8 "chiplets" with 8 cores each:
AMD on Tuesday formally announced its next-generation EPYC processor code-named Rome. The new server CPU will feature up to 64 cores featuring the Zen 2 microarchitecture, thus providing at least two times higher performance per socket than existing EPYC chips.
As discussed in a separate story covering AMD's new 'chiplet' design approach, AMD EPYC 'Rome' processor will carry multiple CPU chiplets manufactured using TSMC's 7 nm fabrication process as well as an I/O die produced at a 14 nm node. As it appears, high-performance 'Rome' processors will use eight CPU chiplets offering 64 x86 cores in total.
Separating CPU chiplets from the I/O die has its advantages because it enables AMD to make the CPU chiplets smaller as physical interfaces (such as DRAM and Infinity Fabric) do not scale that well with shrinks of process technology. Therefore, instead of making CPU chiplets bigger and more expensive to manufacture, AMD decided to incorporate DRAM and some other I/O into a separate chip. Besides lower costs, the added benefit that AMD is going to enjoy with its 7 nm chiplets is ability to easier[sic] bin new chips for needed clocks and power, which is something that is hard to estimate in case of servers.
AMD also announced that Zen 4 is under development. It could be made on a "5nm" node, although that is speculation. The Zen 3 microarchitecture will be made on TSMC's N7+ process ("7nm" with more extensive use of extreme ultraviolet lithography).
AMD's Epyc CPUs will now be offered on Amazon Web Services.
AnandTech live blog of New Horizon event.
Previously: AMD Epyc 7000-Series Launched With Up to 32 Cores
TSMC Will Make AMD's "7nm" Epyc Server CPUs
Intel Announces 48-core Xeons Using Multiple Dies, Ahead of AMD Announcement
Related: Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option
Oracle Offers Servers with AMD's Epyc to its Cloud Customers
(Score: 2) by takyon on Wednesday November 07 2018, @04:53AM (1 child)
Intel may have also played around in order to claim a "3.4x" improvement [arstechnica.com] over the older Epyc with its 48-core Xeon. See update on this article. [tomshardware.com]
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 1, Interesting) by Anonymous Coward on Wednesday November 07 2018, @10:45AM
From what I can tell ( https://www.phoronix.com/scan.php?page=article&item=6-linux-eoy2017&num=7 [phoronix.com] ), a consumer needs to use a specialized distro and a limited selection of libraries that Intel is optimizing for you to enjoy the benefits. Once we're talking about running a specific piece of software you maintain yourself, you can match Intel's optimized assembly with AMD optimized assembly for 99.999% of the use cases and would, regardless, be better off with GPU compute.
(Score: 1, Interesting) by Anonymous Coward on Wednesday November 07 2018, @06:50AM (3 children)
This had 5"x5" 'chips' that housed up to 100 actual chips. Each module had a water cooled jacket and up to a 56 layer "back plane" the chips talked through. It was build to increase the speed and size of 270 family line. It is also one of the "freak-out" techs that Apple and Motorola saw when they three computer worked for 68000 series processor and motherboard.
Looking for a Scientific America from the late 1970's / early 1980's that talked about the tech in more detail.
(Score: 4, Informative) by takyon on Wednesday November 07 2018, @07:05AM (2 children)
AMD's CEO Lisa Su used to be Director of Emerging Products at IBM.
Ryzen uses simultaneous multithreading [wikipedia.org], which was developed at IBM way back in 1968.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 0) by Anonymous Coward on Wednesday November 07 2018, @07:23AM (1 child)
Yup everything old is new again.
Now if INTEL and AMD will get multiple byte (256 to 32k) in a single instruction charged with a single clock "tick". That was nice of earlier IBM ASM. Reality it was microcode running a loop, but it was set up and ran ran as single assembly instruction (like MV(255) from,to compiled up to 6 total bytes (4 bytes if reg to reg pointing). Allowed for every tight code size and simple to read. When I started it 64kB was largest a program coude compile to, but on some of my ealry machines (System 3) we had 12kB of total storage.
(Score: 2, Funny) by Anonymous Coward on Wednesday November 07 2018, @12:40PM
I wanna be new again [sigh]
(Score: 3, Insightful) by Anonymous Coward on Wednesday November 07 2018, @10:58AM
This amd vs intel story is like a textbook argument in favor of competition. Simultaneously, it also shows how a monopoly position naturally leads to stagnation, which in turn opens the door to competition. I think it is also a good case of c-level actual "diversity" (merit based) vs c-level lipservice to diversity (identity based). Theres just so many interesting angles here.
(Score: 0) by Anonymous Coward on Wednesday November 07 2018, @05:30PM
and they won't sell you an epyc chip without their closed source management BS/backdoor.
(Score: 3, Funny) by bob_super on Wednesday November 07 2018, @06:59PM
"Move the memory controller inside the chip"
"Okay, I put it on the die"
"I want more of them"
"Okay, but it's gonna cause you to have a huge chip, bad yields"
"Fine, use multiple chips"
"Now you get asymmetric latency"
"Ok, let's pull th controller back off-die"
"Can I keep it in the chip?"
"Sure, the chip is the new PCB, as the embedded guys already know"