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posted by martyb on Wednesday November 07 2018, @04:49AM   Printer-friendly
from the moah-powah dept.

AMD has announced the next generation of its Epyc server processors, with up to 64 cores (128 threads) each. Instead of an 8-core "core complex" (CCX), AMD's 64-core chips will feature 8 "chiplets" with 8 cores each:

AMD on Tuesday formally announced its next-generation EPYC processor code-named Rome. The new server CPU will feature up to 64 cores featuring the Zen 2 microarchitecture, thus providing at least two times higher performance per socket than existing EPYC chips.

As discussed in a separate story covering AMD's new 'chiplet' design approach, AMD EPYC 'Rome' processor will carry multiple CPU chiplets manufactured using TSMC's 7 nm fabrication process as well as an I/O die produced at a 14 nm node. As it appears, high-performance 'Rome' processors will use eight CPU chiplets offering 64 x86 cores in total.

Why chiplets?

Separating CPU chiplets from the I/O die has its advantages because it enables AMD to make the CPU chiplets smaller as physical interfaces (such as DRAM and Infinity Fabric) do not scale that well with shrinks of process technology. Therefore, instead of making CPU chiplets bigger and more expensive to manufacture, AMD decided to incorporate DRAM and some other I/O into a separate chip. Besides lower costs, the added benefit that AMD is going to enjoy with its 7 nm chiplets is ability to easier[sic] bin new chips for needed clocks and power, which is something that is hard to estimate in case of servers.

AMD also announced that Zen 4 is under development. It could be made on a "5nm" node, although that is speculation. The Zen 3 microarchitecture will be made on TSMC's N7+ process ("7nm" with more extensive use of extreme ultraviolet lithography).

AMD's Epyc CPUs will now be offered on Amazon Web Services.

AnandTech live blog of New Horizon event.

Previously: AMD Epyc 7000-Series Launched With Up to 32 Cores
TSMC Will Make AMD's "7nm" Epyc Server CPUs
Intel Announces 48-core Xeons Using Multiple Dies, Ahead of AMD Announcement

Related: Cray CS500 Supercomputers to Include AMD's Epyc as a Processor Option
Oracle Offers Servers with AMD's Epyc to its Cloud Customers


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  • (Score: 2) by takyon on Wednesday November 07 2018, @04:53AM (1 child)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Wednesday November 07 2018, @04:53AM (#758837) Journal

    https://arstechnica.com/gadgets/2018/11/amd-outlines-its-future-7nm-gpus-with-pcie-4-zen-2-zen-3-zen-4/ [arstechnica.com]

    Zen 2 will also address certain weak aspects of the original Zen. For example, the original Zen used 128-bit data paths to handle 256-bit AVX2 operations; each operation was split into two parts and processed sequentially. In workloads using AVX2, this gave Intel, with its native 256-bit implementation, a huge advantage. Zen 2 doubles the floating-point execution units and data paths to be 256-bit, doubling the bandwidth available and greatly improving the performance of this code. For integer workloads, branch prediction and prefetching have been made more accurate, and some caches enlarged.

    Zen 2 will also offer improved hardware protection against some variants of the Spectre attacks.

    Intel may have also played around in order to claim a "3.4x" improvement [arstechnica.com] over the older Epyc with its 48-core Xeon. See update on this article. [tomshardware.com]

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  • (Score: 1, Interesting) by Anonymous Coward on Wednesday November 07 2018, @10:45AM

    by Anonymous Coward on Wednesday November 07 2018, @10:45AM (#758899)

    In workloads using AVX2, this gave Intel, with its native 256-bit implementation, a huge advantage

    From what I can tell ( https://www.phoronix.com/scan.php?page=article&item=6-linux-eoy2017&num=7 [phoronix.com] ), a consumer needs to use a specialized distro and a limited selection of libraries that Intel is optimizing for you to enjoy the benefits. Once we're talking about running a specific piece of software you maintain yourself, you can match Intel's optimized assembly with AMD optimized assembly for 99.999% of the use cases and would, regardless, be better off with GPU compute.