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Intel Lakefield is based around Foveros technology which helps connect chips and chiplets in a single package that matches the functionality and performance of a monolithic SOC. Each die is then stacked using FTF micro-bumps on the active interposer through which TSVs are drilled to connect with solder bumps and eventually the final package. The whole SOC is just 12×12 (mm) which is 144mm2.
Talking about the SOC itself and its individual layers, the Lakefield SOC that has been previewed consists of at least four layers or dies, each serving a different purpose. The top two layers are composed of the DRAM which will supplement the processor as the main system memory. This is done through the PoP (Package on Package) memory layout which stacks two BGA DRAMs on top of each other as illustrated in the preview video. The SOC won't have to rely on socketed DRAM in this case which saves a lot of footprint on the main board.
The second layer is the Compute Chiplet with a Hybrid CPU architecture and graphics, based on the 10nm process node. The Hybrid CPU architecture has a total of five individual Cores, one of them is labeled as the Big Core which features the Sunny Cove architecture. That's the same CPU architecture that will be featured on Intel's upcoming 10nm Ice Lake processors. The Sunny Cove Core is optimized for high-performance throughput. There are also four small CPUs that are based on the 10nm process but optimized for power efficiency. The same die [has] Intel's Gen 11 graphics engine with 64 Execution Units.
[...] [Last] of all is the base die which serves as the cache and I/O block of the SOC. Labeled as the P1222 and based on a 22FFL process node, the base die comes with a low cost and low leakage design while providing a feature-rich array of I/O capabilities.
It would be nice to finally see some consumer CPUs with stacked DRAM, although the amount was not specified (8 GB?).
Intel video (1m48s). Also at Notebookcheck.
Previously: Intel Announces "Sunny Cove", Gen11 Graphics, Discrete Graphics Brand Name, 3D Packaging, and More
Intel Promises "10nm" Chips by the End of 2019, and More
(Score: 1, Insightful) by Anonymous Coward on Saturday March 02 2019, @09:57PM (5 children)
Any reason one couldn't have a layer of heatsink between functional layers which connects to a larger traditional heatsink and then bump the number of layers up for a silly number of cores?
Don't trust the dust BTW, it hasn't been dust for a while now.
(Score: 1) by knarf on Saturday March 02 2019, @10:44PM (1 child)
Instead of a heat sink I'd put channels in the chip to circulate some form of coolant to deposit heat to the perimeter from where it can be picked up by a heat pipe or -sink.
(Score: 2) by mhajicek on Sunday March 03 2019, @05:12AM
At that scale viscosity is a bitch. You'll get a lot more heat out conductively.
The spacelike surfaces of time foliations can have a cusp at the surface of discontinuity. - P. Hajicek
(Score: 2) by inertnet on Saturday March 02 2019, @11:37PM
I'm not sure which layers will potentially generate the most heat, but wouldn't it be more logical to put the DRAM between the processing layers? Also because the DRAM doesn't need to be connected to the outside.
(Score: 0) by Anonymous Coward on Sunday March 03 2019, @05:43PM (1 child)
take a BIG sheet of paper. draw your logic gates / transistors (if then else, etc).
then take a picture of it so the picture is tiny.
that's how they make chips. ofc there's some "3d" involved with chemicals and etching and making some crystals grow the right way
and at the right places (vapour deposit).
the whole thing is very very flat and really they are selling you a glorified "photo" that reacts with electrcity.
the process cannot be made like tower with 64 floors. if you're lucky it has 4 floors or such ...
(Score: 2) by takyon on Sunday March 03 2019, @05:46PM
And yet NAND is made with 64 or even 96 layers.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 1, Funny) by Anonymous Coward on Saturday March 02 2019, @10:17PM
Guess they ran out of room for the NSA-approved code on the ground floor, so they had to start building up. Now they have a 3D attack surface.
(Score: 2) by Snotnose on Sunday March 03 2019, @12:53AM
Qualcomm was doing this with SC1x and SC2x chips 10-15 years ago. The goal, if I remember correctly, was to have a chip that wholesaled around $2.50 and would be sold in zillions of phones in India. China wasn't a thing yet. If memory serves (which it doesn't all that often nowdays :( ) it had a baseband chip, a memory chip, an RF chip, and a PMIC, stacked in that order.
The problems? First, how do you get rid of the heat? Easy, you run all the chips at a much lower clock speed than their rated capacity. Second, how do you line up all these connector bumps when the entire chip is smaller than your pinky fingernail? They actually got it working, and working very well. But I left the company before finding out how well they sold.
When the dust settled America realized it was saved by a porn star.
(Score: 0) by Anonymous Coward on Monday March 04 2019, @07:26PM
don't care. give me a trustable CPU or i will buy as old as i can until i can buy riscv or power.