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posted by martyb on Saturday April 06 2019, @07:33PM   Printer-friendly
from the when-will-we-need-to-start-miniaturizing-molecules? dept.

TSMC's 5nm EUV Making Progress: Process design kits, design rule manual, electronic design automation tools, 3rd Party IP Ready

TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.

TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).

[*] TSMC - Taiwan Semiconductor Manufacturing Corporation

Same chip(let) size? Approximately double the core count.

Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April

Related: Samsung Plans to Make "5nm" Chips Starting in 2019-2020
ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019


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  • (Score: 2) by JoeMerchant on Saturday April 06 2019, @10:58PM (4 children)

    by JoeMerchant (3937) on Saturday April 06 2019, @10:58PM (#825536)

    What kind of math is that? Intel 7nm is higher density than TSMC 5nm?

    The more interesting battle might be in multi-layer and full 3D structures. If you can stack 100+ ultra-thin layers, even if the feature size is 20nm, that's going to be extreme density. Even if the cooling problem isn't solved, this kind of structure could do the work of 100s of equivalent 100% duty cycle parts, meaning an instant answer to a hard question - followed by 99% downtime to cool off...

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  • (Score: 0) by Anonymous Coward on Sunday April 07 2019, @01:22AM (1 child)

    by Anonymous Coward on Sunday April 07 2019, @01:22AM (#825582)

    nm chip die sizes are marketing bullshit these days. Intel and TSMC measure different things.

    • (Score: 2) by DannyB on Monday April 08 2019, @01:35PM

      by DannyB (5839) on Monday April 08 2019, @01:35PM (#826140) Journal

      Remember back in the day when everyone compared MHz and later GHz? Isn't an Intel GHz exactly the same thing as an AMD GHz? And aren't they exactly the same and consistent even within a single manufacturer's product lines?

      What? No!?!?!

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  • (Score: 2) by takyon on Sunday April 07 2019, @03:43AM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Sunday April 07 2019, @03:43AM (#825626) Journal

    As stated, the number is not meaningful, particularly when comparing between Intel, Samsung, TSMC, etc.

    Just think of Intel 14nm++++ as "Intel A v5", Intel 10nm as "Intel B v1". The numbers are just labels. Then you can find the stats to compare various processes. TSMC's 7FF+ supposedly will use 90% of the power of TSMC 7FF, for about the same performance, and 83% of the area for the same amount of transistors. TSMC 5FF is 80% power, 115% performance, and 55% of the area compared to TSMC 7FF. So 5FF should be about 89% power, 115% perf, and 66% area of 7FF+.

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  • (Score: 2) by takyon on Sunday April 07 2019, @12:09PM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Sunday April 07 2019, @12:09PM (#825738) Journal

    About the 3D stuff:

    1. Neuromorphic chips with very low power consumption (due to acting more like the human brain) could benefit first. Layered GPUs could be seen long before CPUs.

    2. A new transistor type [soylentnews.org] (there are several candidates [wikipedia.org]) could reduce heat, making layering feasible.

    3. On-chip optics and DRAM placed close to CPU in 3D structure could help.

    4. Continuing down to/past the limits of lithography (possibly requiring technologies like self-assembly) will be rewarding, improving our ability to create (other) nanotechnologies.

    5. To the extent that the "X-nanometer" labels even mean anything, the industry still has some room to scale down, likely to at least one or two nodes smaller than TSMC's "5nm":

    Transistor Options Beyond 3nm [semiengineering.com]

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