SoylentNews is people
SoylentNews
from the when-will-we-need-to-start-miniaturizing-molecules? dept.
TSMC[*] this week said that it has completed development of tools required for design of SoCs that are made using its 5 nm (CLN5FF, N5) fabrication technology. The company indicated that some of its alpha customers (which use pre-production tools and custom designs) had already started risk production of their chips using its N5 manufacturing process, which essentially means that the technology is on-track for high-volume manufacturing (HVM) in 2020.
TSMC's N5 is the company's 2nd generation fabrication technology that uses both deep ultraviolet (DUV) as well as extreme ultraviolet (EUV) lithography. The process can use EUVL on up to 14 layers (a tangible progress from N7+, which uses EUVL on four non-critical layers) to enable significant improvements in terms of density. TSMC says that when compared to N7 (1st Gen 7 nm, DUV-only), N5 technology will allow chip developers to shrink die area of their designs by ~45%, making transistor density ~1.8x higher. It will also increase frequency by 15% (at the same complexity and power) or reduce power consumption by 20% power reduction (at the same frequency and complexity).
[*] TSMC - Taiwan Semiconductor Manufacturing Corporation
Same chip(let) size? Approximately double the core count.
Previously: TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April
Related: Samsung Plans to Make "5nm" Chips Starting in 2019-2020
ASML Plans to Ship 30 Extreme Ultraviolet Lithography (EUV) Scanners in 2019
(Score: 2) by takyon on Sunday April 07 2019, @12:09PM
About the 3D stuff:
1. Neuromorphic chips with very low power consumption (due to acting more like the human brain) could benefit first. Layered GPUs could be seen long before CPUs.
2. A new transistor type [soylentnews.org] (there are several candidates [wikipedia.org]) could reduce heat, making layering feasible.
3. On-chip optics and DRAM placed close to CPU in 3D structure could help.
4. Continuing down to/past the limits of lithography (possibly requiring technologies like self-assembly) will be rewarding, improving our ability to create (other) nanotechnologies.
5. To the extent that the "X-nanometer" labels even mean anything, the industry still has some room to scale down, likely to at least one or two nodes smaller than TSMC's "5nm":
Transistor Options Beyond 3nm [semiengineering.com]
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]