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At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.
Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.
TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement
Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.
Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production
GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.
Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.
Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."
According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"
There may only be two left, but neither company is sitting still:
- Samsung has already announced 3nm fab plans and released design kits.
- TSMC has gained approval for the construction of a 3nm factory next to its 5nm fab.
Previous Coverage
TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Samsung Plans to Make "5nm" Chips Starting in 2019-2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April
(Score: 0) by Anonymous Coward on Monday June 03 2019, @06:53AM (1 child)
If we could use physical tri-state logic orderly to represent trits instead of bits, density and precision of computations would be proportionally increased. Unfortunately, a Shannon's curse of binary still haunts us, an apparition of two's complement...
(Score: 2) by maxwell demon on Monday June 03 2019, @07:20AM
Unfortunately, a Shannon's curse of binary still haunts us
Shannon used bits as measure of information, not implying that this is what you should use. No, the use of bits is because this allows simpler circuits. A basic NOT gate just needs one transistor. A basic NAND gate needs one transistor per input. I'd suspect that implementing trit gates in hardware is sufficiently complex that it at least negates the savings from needing less of them.
The Tao of math: The numbers you can count are not the real numbers.