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posted by martyb on Monday June 03 2019, @06:14AM   Printer-friendly
from the and-then-there-were-two dept.

At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.

Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.

TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement

Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.

Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production

GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.

Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.

Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."

According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"

There may only be two left, but neither company is sitting still:

Previous Coverage
TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Samsung Plans to Make "5nm" Chips Starting in 2019-2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April


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  • (Score: 5, Informative) by takyon on Monday June 03 2019, @06:54AM (10 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Monday June 03 2019, @06:54AM (#850750) Journal

    TSMC's "6nm" is a denser drop-in for the current "7nm". According to them, it will have no performance and power consumption improvements, just a bit of area scaling. It looks like it will be a bit worse than "7nm+" which uses more EUV, but companies that already developed designs for "7nm" can save a few bucks.

    https://www.anandtech.com/show/14228/tsmc-reveals-6-nm-process-technology-7-nm-with-higher-transistor-density [anandtech.com]

    TSMC states that their N6 fabrication technology offers 18% higher logic density when compared to the company’s N7 process (1st Gen 7 nm, DUV-only), yet offers the same performance and power consumption. Furthermore, according to TSMC N6 'leverages new capabilities in extreme ultraviolet lithography (EUVL)' gained from N7+, but does not disclose how exactly it uses EUV for the particular technology. Meanwhile, N6 uses the same design rules as N7 and enables developers of chips to re-use the same design ecosystem (e.g., tools, etc.), which will enable them to lower development costs. Essentially, N6 allows to shrink die sizes of designs developed using N7 design rules by around 15% while using the familiar IP for additional cost savings.

    "3nm" should be the point when TSMC and Samsung transition to gate-all-around transistors.

    There could be a couple of nodes beyond that before real big changes are needed. Like these [soylentnews.org].

    https://semiengineering.com/transistor-options-beyond-3nm/ [semiengineering.com]
    https://semiengineering.com/big-trouble-at-3nm/ [semiengineering.com] (article was written before GlobalFoundries chickened out of "7nm")

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  • (Score: 2) by janrinok on Monday June 03 2019, @07:29AM

    by janrinok (52) Subscriber Badge on Monday June 03 2019, @07:29AM (#850757) Journal
    We can always rely on you to provide the additional information that many of us don't know. Have a mod point!
  • (Score: 2, Funny) by Anonymous Coward on Monday June 03 2019, @10:42AM (3 children)

    by Anonymous Coward on Monday June 03 2019, @10:42AM (#850789)

    What do you think about apples new $7999.99 wieghtless and completely transparent MacBook?

    • (Score: 3, Funny) by takyon on Monday June 03 2019, @10:59AM (2 children)

      by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Monday June 03 2019, @10:59AM (#850797) Journal

      It uses a 0nm processor, right?

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      • (Score: 0) by Anonymous Coward on Monday June 03 2019, @12:45PM (1 child)

        by Anonymous Coward on Monday June 03 2019, @12:45PM (#850834)

        Yep, 0 nm technology.

        • (Score: 2) by bob_super on Monday June 03 2019, @05:36PM

          by bob_super (1357) on Monday June 03 2019, @05:36PM (#850919)

          Incidentally, 0nm is also the travel on the keyboard they'll put on it.
          "3D haptic feedback", they'll call it. With changeable keyboard shapes.

          Yet it will still fail because of microscopic dust, and it will be your fault.

  • (Score: 2) by Rupert Pupnick on Monday June 03 2019, @02:51PM (4 children)

    by Rupert Pupnick (7277) on Monday June 03 2019, @02:51PM (#850861) Journal

    Good stuff, thanks. So the question becomes how useful is just area scaling alone to customers that would be designing these parts into their products. Depends of course on the application, and whether you run into thermal or power consumption issues.

    • (Score: 2) by bob_super on Monday June 03 2019, @05:43PM (3 children)

      by bob_super (1357) on Monday June 03 2019, @05:43PM (#850922)

      Almost all chips can handle having a thermal interface to the copper that's 18% smaller. The problem is usually interfacing the copper to air.
      Intel would have to stop using dumb paste, but that's about it.

      On the other hand, 18% chip size reduction means significantly higher yields (more dies per wafer if constant impurities).

      While the transistors don't change, calling 6 instead 7 is actually a reasonable approach, for once.
      On the other hand, having 5nm, 6nm, 7nm, 10nm (even before Intel goes 10nm++UltraTurboAlphaPrime) is going to be confusing for anyone not knee-deep in that industry.

      • (Score: 2) by takyon on Monday June 03 2019, @08:38PM (2 children)

        by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Monday June 03 2019, @08:38PM (#850984) Journal

        If there aren't any thermal problems, more chiplets could be stuffed onto a board. Epyc uses 8 for 64 cores, rumor has it that it could be increased to 10+.

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        • (Score: 2) by bob_super on Monday June 03 2019, @08:51PM (1 child)

          by bob_super (1357) on Monday June 03 2019, @08:51PM (#850992)

          You can keep adding chiplets as long as you find a way to bring more Amps in, and take more Watts out, of the socket.
          The chiplet size is not the most important factor. Cu is a great conductor, and solder is pretty good. Intel caused trouble with their shitty solder paste, making big die sizes actually better, but using proper methods, the conductivity is so much better that die size is nowhere near the system's limiting factor.

          You also need to make sure you don't put too many chiplets on the shared resources, or have more shared resources to avoid starvation. Each chiplet requires a good deal of connectivity, so you end up needing two separate IO chips, a small one for the cheap stuff, and a bit one to enable the extra connections. That's got a non-trivial cost.