At the end of March, two semiconductor manufacturing titans climbed another rung on the ladder of Moore's Law.
Taiwan Semiconductor (TSMC) announced 5nm manufacturing of at-risk-production while Samsung announced its own 5nm manufacturing process was ready for sampling.
TSMC says its 5-nm process offers a 15 percent speed gain or a 30 percent improvement in power efficiency. Samsung is promising a 10 percent performance improvement or a 20 percent efficiency improvement
Also, "both Samsung and TSMC are offering what they're calling a 6-nm process" as a kind of stepping stone for customers with earlier availability (H2 2019) vs 5nm production.
Unfortunately, but perhaps not unexpectedly, the playing field has narrowed significantly with the progression to 5nm foundry production
GlobalFoundries gave up at 14 nm and Intel, which is years late with its rollout of an equivalent to competitors' 7 nm, is thought to be pulling back on its foundry services, according to analysts.
Samsung and TSMC remain because they can afford the investment and expect a reasonable return. Samsung was the largest chipmaker by revenue in 2018, but its foundry business ranks fourth, with TSMC in the lead. TSMC's capital expenditure was $10 billion in 2018. Samsung expects to nearly match that on a per-year basis until 2030.
Can the industry function with only two companies capable of the most advanced manufacturing processes? "It's not a question of can it work?" says [G. Dan Hutcheson, at VLSI Research]. "It has to work."
According to Len Jelinek, a semiconductor-manufacturing analyst at IHS Markit. "As long as we have at least two viable solutions, then the industry will be comfortable"
There may only be two left, but neither company is sitting still:
Previous Coverage
TSMC's "5nm" (CLN5FF) Process On-Track for High-Volume Manufacturing in 2020
TSMC Holds Groundbreaking Ceremony for "5nm" Fab, Production to Begin in 2020
Samsung Plans to Make "5nm" Chips Starting in 2019-2020
TSMC Details Scaling/Performance Gains Expected From "5nm CLN5" Process
TSMC Tapes Out Second-Generation "7nm" Chip Using EUV, Will Begin Risk Production of "5nm" in April
(Score: 2) by bob_super on Monday June 03 2019, @08:51PM (1 child)
You can keep adding chiplets as long as you find a way to bring more Amps in, and take more Watts out, of the socket.
The chiplet size is not the most important factor. Cu is a great conductor, and solder is pretty good. Intel caused trouble with their shitty solder paste, making big die sizes actually better, but using proper methods, the conductivity is so much better that die size is nowhere near the system's limiting factor.
You also need to make sure you don't put too many chiplets on the shared resources, or have more shared resources to avoid starvation. Each chiplet requires a good deal of connectivity, so you end up needing two separate IO chips, a small one for the cheap stuff, and a bit one to enable the extra connections. That's got a non-trivial cost.
(Score: 2) by takyon on Monday June 03 2019, @11:24PM
I allude to these rumors:
AMD Milan Rumor: ~80 Cores, Combined With GPUs + HBM [soylentnews.org]
If AMD chooses not to use the "6nm" node and uses "7nm+" instead, they could take advantage of power efficiency improvements.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]