Stories
Slash Boxes
Comments

SoylentNews is people

posted by martyb on Wednesday July 24 2019, @02:33PM   Printer-friendly
from the imagine-a-beowolf-cluster-of-these...on-a-chip! dept.

First 3D Nanotube and RRAM ICs Come Out of Foundry

Here's something you don't see very often at government-sponsored technology meetings—spontaneous applause. It happened at DARPA's Electronics Resurgence Initiative Summit this week when MIT assistant professor Max Shulaker held up a silicon wafer that is the first step in proving DARPA's plan to turn a trailing edge foundry into something that can produce chips that can compete—even in a limited sense—with the world's leading edge foundries.

"This wafer was made just last Friday... and it's the first monolithic 3D IC ever fabricated within a foundry," he told the crowd of several hundred engineers Tuesday in Detroit. On the wafer were multiple chips made of a layer of CMOS carbon nanotube transistors and a layer of RRAM memory cells built atop one another and linked together vertically with a dense array of connectors called vias. The idea behind the DARPA-funded project, called 3DSoC, is that chips made with multiple layers of both would have a 50-fold performance advantage over today's 7-nanometer chips. That's especially ambitious given that the lithographic process the new chips are based on (the 90-nanometer node) was last cutting-edge back in 2004.

The project is only about a year old, but by the end of its 3.5-year run, DARPA wants a foundry technology that makes chips with 50-million logic gates, 4 gigabytes of nonvolatile memory, and 9 million interconnects per square millimeter between the layers that can transmit 50 terabits per second while consuming less than 2 picojoules per bit.

What Shulaker showed on Tuesday can't do all that yet, of course. But it's a key milestone in that journey. Together with SkyWater Technology Foundry and other partners "we've completely reinvented how we manufacture this technology, transforming it from a technology that only worked in our academic labs to a technology that can and is already today working inside a commercial fabrication facility within a U.S. foundry," he said.

Here's the paper I've linked a dozen times in the last year.


Original Submission

 
This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 2) by Alfred on Wednesday July 24 2019, @03:22PM (4 children)

    by Alfred (4006) on Wednesday July 24 2019, @03:22PM (#870703) Journal
    I would expect the CPU layers to generate significantly more heat then the flash layers. I imagine the middle layers will be nice and toasty so cooling could be an issue unless they are going to thermally throttle it. Could work great as long as apple doesn't do the thermal design.

    Like any specs they will be misleading

    transmit 50 terabits per second while consuming less than 2 picojoules per bit.

    What do they mean by transmit? I thought they meant moving data in the chip, maybe thats not it. 50Tbit(10E12)*2pJ(10E-12) = 100 Joules/sec = 100 watts. Just to move data? That seems off. I doubt my desktop CPU, without the advantage of on die communication, uses that much to talk to RAM. So how much more when we add CPU consumption? Maybe they are looking to that as a burst rate and not continuous.

    Either way, specs are misleading

    Starting Score:    1  point
    Karma-Bonus Modifier   +1  

    Total Score:   2  
  • (Score: 2) by takyon on Wednesday July 24 2019, @03:31PM (3 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Wednesday July 24 2019, @03:31PM (#870707) Journal

    That refers to memory bandwidth between the CPU and integrated DRAM. See page 5:

    Memory Access Parameter / 2D / 3D TSV Package / 3DSoC
    Total I/O / 512 / 1K / 33K
    Max Bandwidth (Gb/s) / 400 / 1K / 46K
    Memory access energy (pJ/bit) / 52 / 32 / 1.5
    VDD (Volts System) / 1.6 / 1.2 / 0.6

    46K Gb/s = 46 terabits per second

    The advantage here is that by shortening the distance data has to travel from the CPU to the DRAM, you can get incredible performance increases and reduce the energy needed.

    --
    [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
    • (Score: 2) by Alfred on Wednesday July 24 2019, @08:08PM (2 children)

      by Alfred (4006) on Wednesday July 24 2019, @08:08PM (#870839) Journal
      Right. Crazy good transfer speeds. But unless I got my math wrong, 100W is a lot for that.
      • (Score: 2) by takyon on Wednesday July 24 2019, @08:47PM

        by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Wednesday July 24 2019, @08:47PM (#870864) Journal

        They say that it "dissipates < 500mW of average operating power" so that's what I'm going to go with.

        --
        [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
      • (Score: 2) by sgleysti on Thursday July 25 2019, @12:07AM

        by sgleysti (56) Subscriber Badge on Thursday July 25 2019, @12:07AM (#870904)

        Since they call the 2pJ/bit metric "memory access energy", I'm guessing this is the energy to read one bit of the nonvolatile memory. Since this is specified at 4GB = 32Gb, it would take 2pJ/bit * 32Gb = 64mJ to read the entire memory on the chip once.

        If that's all that metric means, it is orthogonal to the power required for the 50Tb/s transmission bandwidth, and the summary is just confusing. This is my best guess.