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from the imagine-a-beowolf-cluster-of-these...on-a-chip! dept.
First 3D Nanotube and RRAM ICs Come Out of Foundry
Here's something you don't see very often at government-sponsored technology meetings—spontaneous applause. It happened at DARPA's Electronics Resurgence Initiative Summit this week when MIT assistant professor Max Shulaker held up a silicon wafer that is the first step in proving DARPA's plan to turn a trailing edge foundry into something that can produce chips that can compete—even in a limited sense—with the world's leading edge foundries.
"This wafer was made just last Friday... and it's the first monolithic 3D IC ever fabricated within a foundry," he told the crowd of several hundred engineers Tuesday in Detroit. On the wafer were multiple chips made of a layer of CMOS carbon nanotube transistors and a layer of RRAM memory cells built atop one another and linked together vertically with a dense array of connectors called vias. The idea behind the DARPA-funded project, called 3DSoC, is that chips made with multiple layers of both would have a 50-fold performance advantage over today's 7-nanometer chips. That's especially ambitious given that the lithographic process the new chips are based on (the 90-nanometer node) was last cutting-edge back in 2004.
The project is only about a year old, but by the end of its 3.5-year run, DARPA wants a foundry technology that makes chips with 50-million logic gates, 4 gigabytes of nonvolatile memory, and 9 million interconnects per square millimeter between the layers that can transmit 50 terabits per second while consuming less than 2 picojoules per bit.
What Shulaker showed on Tuesday can't do all that yet, of course. But it's a key milestone in that journey. Together with SkyWater Technology Foundry and other partners "we've completely reinvented how we manufacture this technology, transforming it from a technology that only worked in our academic labs to a technology that can and is already today working inside a commercial fabrication facility within a U.S. foundry," he said.
Here's the paper I've linked a dozen times in the last year.
(Score: 2) by sgleysti on Thursday July 25 2019, @12:07AM
Since they call the 2pJ/bit metric "memory access energy", I'm guessing this is the energy to read one bit of the nonvolatile memory. Since this is specified at 4GB = 32Gb, it would take 2pJ/bit * 32Gb = 64mJ to read the entire memory on the chip once.
If that's all that metric means, it is orthogonal to the power required for the 50Tb/s transmission bandwidth, and the summary is just confusing. This is my best guess.