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posted by Fnord666 on Wednesday December 11 2019, @08:09AM   Printer-friendly
from the small-roads-on-that-map dept.

Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm

One of the interesting disclosures here at the IEEE International Electron Devices Meeting (IEDM) has been around new and upcoming process node technologies. Almost every session so far this week has covered 7nm, 5nm, and 3nm processes (as the industry calls them). What we didn't expect to see disclosed was an extended roadmap of Intel's upcoming manufacturing processes.

[...] Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021, then 5nm in 2023, 3nm in 2025, 2nm in 2027, and 1.4 nm in 2029. This is the first mention on 1.4nm for Intel on any slide, so this confirms where Intel is going, and just for context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.

It is perhaps worth noting that some of the talks at this year's IEDM features dimensions on the order of 0.3nm with what are called '2D self-assembly' materials, so something this low isn't unheard of, but it is unheard of in silicon. Obviously there are many issues going that small that Intel (and its partners) will have to overcome.

Inbetween each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. Intel believes they can do this on a yearly cadence, but also have overlapping teams to ensure that one full process node can overlap with another.

The interesting element to this slide is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older '++' version of a process node in the same timeframe. Despite Intel stating that they are disaggregating chip design from process node technology, at some point there has to be a commitment to a process node in order to start the layouts in silicon. At that point the process node procedure is kind of locked, especially when it goes to mask creation.


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  • (Score: 2) by FatPhil on Wednesday December 11 2019, @02:20PM (4 children)

    by FatPhil (863) <pc-soylentNO@SPAMasdf.fi> on Wednesday December 11 2019, @02:20PM (#931043) Homepage
    "if that 1.4nm is indicative of any actual feature"

    The "X nm" nomenclature hasn't corresponded to any feature for about a decade. There was an agreement that a 29% reduction in the linear scale denoting the technology wasn't convincing the punters that the density had doubled. (0.71*0.71 = 0.5), and therefore they should adopt an abstract quantity, with linear units, to denote a property which has squared units, so that doubling looked like doubling to punters who buy things purely because of abstract numbers printed on the side of the box rather than physical measurements of how well it solves the problem that needs solving (time and energy required).

    Here's a good summary of how things stand in reality, it's barely out of date as most things since, like this story, are slideware:
        https://www.techcenturion.com/7nm-10nm-14nm-fabrication
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  • (Score: 3, Interesting) by takyon on Wednesday December 11 2019, @02:40PM (3 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Wednesday December 11 2019, @02:40PM (#931051) Journal

    If you do the math on the node numbers, you would expect density to double:

    142 / 102 = 1.96
    102 / 72 = 2.04081632653

    Intel's new CEO blamed the company [pcgamer.com] for pursuing a 2.7x transistor density increase on the "10nm" node, instead of 2x.

    Intel likes to tout transistors per mm2 [soylentnews.org] (when favorable).

    The node number doesn't give you other info, like potential performance or efficiency gains [anandtech.com].

    If "1.4nm" ends up being representative of anything and Intel can actually get it to work, then we'll see some unspecified but great transistor density increases. If not from Intel, then TSMC, Samsung, SMIC (China), or others can do it. "1.4nm" presumably is not a theoretical limit, since single-atom transistors are possible [wikipedia.org].

    After that, pray for femtocomputing [kurzweilai.net].

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    • (Score: 2) by FatPhil on Wednesday December 11 2019, @11:19PM (2 children)

      by FatPhil (863) <pc-soylentNO@SPAMasdf.fi> on Wednesday December 11 2019, @11:19PM (#931260) Homepage
      > If you do the math on the node numbers, you would expect density to double:

      You've completely missed my point, and the industry marketroids' point. In order to express "double density", they feel the need to use a half-sized linear number, so that people who *don't do the maths* will view it as a doubling. That's a consciously made, and publicly stated, decision. Doing the maths will only lead to confusion, don't do that. Someone should have told you this a decade ago, goodness knows how much marketting bullshit you've swallowed in that time.
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