Stories
Slash Boxes
Comments

SoylentNews is people

posted by Fnord666 on Wednesday December 11 2019, @08:09AM   Printer-friendly
from the small-roads-on-that-map dept.

Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm

One of the interesting disclosures here at the IEEE International Electron Devices Meeting (IEDM) has been around new and upcoming process node technologies. Almost every session so far this week has covered 7nm, 5nm, and 3nm processes (as the industry calls them). What we didn't expect to see disclosed was an extended roadmap of Intel's upcoming manufacturing processes.

[...] Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021, then 5nm in 2023, 3nm in 2025, 2nm in 2027, and 1.4 nm in 2029. This is the first mention on 1.4nm for Intel on any slide, so this confirms where Intel is going, and just for context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.

It is perhaps worth noting that some of the talks at this year's IEDM features dimensions on the order of 0.3nm with what are called '2D self-assembly' materials, so something this low isn't unheard of, but it is unheard of in silicon. Obviously there are many issues going that small that Intel (and its partners) will have to overcome.

Inbetween each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. Intel believes they can do this on a yearly cadence, but also have overlapping teams to ensure that one full process node can overlap with another.

The interesting element to this slide is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older '++' version of a process node in the same timeframe. Despite Intel stating that they are disaggregating chip design from process node technology, at some point there has to be a commitment to a process node in order to start the layouts in silicon. At that point the process node procedure is kind of locked, especially when it goes to mask creation.


Original Submission

 
This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 2) by HiThere on Wednesday December 11 2019, @04:52PM (1 child)

    by HiThere (866) on Wednesday December 11 2019, @04:52PM (#931123) Journal

    Unfortunately, it's Intel, so we can expect the numbers to be manipulated or faked when they start selling them. And a whole **** of new exploits.

    --
    Javascript is what you use to allow unknown third parties to run software you have no idea about on your computer.
    Starting Score:    1  point
    Karma-Bonus Modifier   +1  

    Total Score:   2  
  • (Score: 2) by takyon on Wednesday December 11 2019, @05:01PM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Wednesday December 11 2019, @05:01PM (#931127) Journal

    I have no plans to buy Intel. If they pull something out of their hat and manage to leapfrog AMD in perf/$, I'll just wait a few months for AMD to make a comeback or cut prices.

    Then there's ARM (got 2x RasPi4B), RISC-V and otherz.

    --
    [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]