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posted by martyb on Thursday February 20 2020, @04:11PM   Printer-friendly

Scientists at Tokyo Institute of Technology (Tokyo Tech) and Socionext Inc. have designed the world's smallest all-digital phase-locked loop (PLL). PLLs are critical clocking circuits in virtually all digital applications, and reducing their size and improving their performance is a necessary step to enabling the development of next-generation technologies.

[...] The entire all-digital PLL fits in a 50 × 72 μm2 region, making it the smallest PLL to date.

A core building block of SoC devices is the phase-locked loop (PLL), a circuit that synchronizes with the frequency of a reference oscillation and outputs a signal with the same or higher frequency.

PLLs generate 'clocking signals', whose oscillations act as a metronome that provides a precise timing reference for the harmonious operation of digital devices.

[...] Manufacturers have been racing to develop increasingly smaller semiconductors. 7 nm semiconductors (a massive improvement over their 10 nm predecessor) are already in production, and methods to build 5 nm ones are now being looked at.

However, in this endeavor stands a major bottleneck. Existing PLLs require analog components, which are generally bulky and have designs that are difficult to scale down.

Scientists at Tokyo Tech and Socionext Inc., led by Prof. Kenichi Okada, have addressed this issue by implementing a 'synthesizable' fractional-N PLL, which only requires digital logic gates, and no bulky analog components, making it easy to adopt in conventional miniaturized integrated circuits.


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  • (Score: 2, Funny) by dwilson on Thursday February 20 2020, @05:01PM (8 children)

    by dwilson (2599) on Thursday February 20 2020, @05:01PM (#960348)

    7 nm semiconductors (a massive improvement over their 10 nm predecessor)

    So 3 nanometres is massive now, is it. Must be the same logic that newspapers use when they print a headline like "Stock at company X plunges after event Y" and it dropped by a whopping 0.37%. Or when a new technology is described as a quantum leap ahead of it's predecessor, and they actually meant big/huge.

    Context is everything, I guess.

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    • (Score: 2) by tizan on Thursday February 20 2020, @06:17PM

      by tizan (3245) on Thursday February 20 2020, @06:17PM (#960378)

      Yes when you are so close to the quantum limit !

    • (Score: 4, Insightful) by Freeman on Thursday February 20 2020, @06:23PM (6 children)

      by Freeman (732) on Thursday February 20 2020, @06:23PM (#960381) Journal

      Going from 10nm to 7nm is a huge improvement when think about the scale. It's a 70% improvement over the previous generation. Now, just think, if your next combustion engine car needed 70% less gas to get from point a to point b. That would be a huge improvement.

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      • (Score: 3, Funny) by Freeman on Thursday February 20 2020, @06:27PM (5 children)

        by Freeman (732) on Thursday February 20 2020, @06:27PM (#960384) Journal

        I think I mathed that wrong, that would be a 30% improvement. Just chock it up to the marketing department.

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        • (Score: 2) by takyon on Thursday February 20 2020, @06:36PM (3 children)

          by takyon (881) <takyonNO@SPAMsoylentnews.org> on Thursday February 20 2020, @06:36PM (#960393) Journal

          Even minor 5-10% efficiency improvements would be massive in many industries, impacting trillions of dollars of commerce.

          But the cat is out of the bag. There is going to be a 1,000x improvement within the next decade from 3DSoC or another monolithic 3D design. Everything we're buying today is hot trash.

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          • (Score: 2) by Freeman on Thursday February 20 2020, @08:14PM (1 child)

            by Freeman (732) on Thursday February 20 2020, @08:14PM (#960425) Journal

            That's quite interesting. Seems like, so long as VR can hang in there for a while longer, viable hardware for super awesome all-in-one VR headsets is around the corner, then.

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            • (Score: 2) by takyon on Friday February 21 2020, @04:53AM

              by takyon (881) <takyonNO@SPAMsoylentnews.org> on Friday February 21 2020, @04:53AM (#960588) Journal

              Depends on how you define "around the corner", but in general I agree. All of the computation will be done locally in an untethered headset (the kind of headset that typically uses Qualcomm Snapdragon chips today) and resolution + framerates will skyrocket. Up to 16K resolution over a ~200° horizontal FOV at 1000 Hz should be the end goal.

              In the case of VR you have foveated rendering and other optimizations that could reduce necessary GPU performance by over 90% [roadtovr.com]. I think this could rise to 98% for a 16K panel where only a tiny amount of the screen needs to be rendered at 16K at any given frame.

              AR will definitely see benefits with 3DSoC. One of the first things the collaboration built was a real-time imaging chip: https://youtu.be/6ir_--MgMJI?t=1198 [youtu.be]

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          • (Score: 2) by RamiK on Friday February 21 2020, @05:31AM

            by RamiK (1813) on Friday February 21 2020, @05:31AM (#960603)

            There is going to be a 1,000x improvement within the next decade from 3DSoC or another monolithic 3D design.

            Caveat emptor: MonolithIC3D were talking about a 1,000x improvement circa mid-2018 using (then) contemporary manufacturing techniques when DARPA was looking where to put their $75 million grant money.

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        • (Score: 1, Interesting) by Anonymous Coward on Thursday February 20 2020, @11:05PM

          by Anonymous Coward on Thursday February 20 2020, @11:05PM (#960484)

          They mostly deal in areas, so it is 30%^2. About 50% really, or twice as many components per square mm

  • (Score: 4, Interesting) by Dr Spin on Thursday February 20 2020, @05:29PM (4 children)

    by Dr Spin (5239) on Thursday February 20 2020, @05:29PM (#960359)

    Some existing PLLs may require analog components, but the concept of a digital one is not exactly new. I used a digital PLL with no analogue components to make a data separator for ST506 using SSI TTL in about 1980, and, AFAICT, that was 40 years ago. I am not sure the concept was even new when I did it.

    I think I used a COTS phase-lock system with programmable divide by N or N+1 in a frequency agile selective calling radio design around that time too. It was able to transmit or receive any frequency in steps of 25kHz across Band II by programming the division ratio. (Miy own one could - customers had an EPROM that could only use frequencies they had the legal right to use).

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    • (Score: 3, Interesting) by PartTimeZombie on Thursday February 20 2020, @09:24PM (2 children)

      by PartTimeZombie (4827) Subscriber Badge on Thursday February 20 2020, @09:24PM (#960452)

      1980 was 10 years ago.

      • (Score: 0) by Anonymous Coward on Friday February 21 2020, @01:08AM

        by Anonymous Coward on Friday February 21 2020, @01:08AM (#960533)

        Yet 1984 is still coming next year ...

      • (Score: 0) by Anonymous Coward on Friday February 21 2020, @06:04AM

        by Anonymous Coward on Friday February 21 2020, @06:04AM (#960612)

        Only in New Zealand and Queensland.

    • (Score: 0) by Anonymous Coward on Friday February 21 2020, @01:53AM

      by Anonymous Coward on Friday February 21 2020, @01:53AM (#960551)

      Some existing PLLs may require analog components, but the concept of a digital one is not exactly new.

      The fact that was integrated on the same circuit (so you don't have access to the analog part) doesn't necessary make it entirely digital.
      Those VCO-s exclusively in digital (no ADC/DAC involved) are a pain.

      Not totally related, but there you have it: just 2% helium in the environ will kill your iPhone [youtube.com] (it will recover after some days).
      Has to do with the use of microelectromechanical oscillators [wikipedia.org] (a tuning fork carved in silicon) because of a smaller footprint than a quartz oscillator. Turns out helium diffuses in silicon and strongly alters the resonance frequency.

  • (Score: 1, Redundant) by Rupert Pupnick on Thursday February 20 2020, @09:21PM

    by Rupert Pupnick (7277) on Thursday February 20 2020, @09:21PM (#960449) Journal

    This really isn't new technology. The first digital PLLs I worked with were in FibreChannel Arbitrated Loop transceivers for clock recovery in the mid 1990's that recovered 1 Gb/s serial data. Today, pretty much anywhere you have a high speed serial data stream, there's an IC with an embedded digital PLL at the end of it.

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