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TSMC Has Started The Development of The 2nm Lithography Process
Earlier this month, we saw that TSMC was getting its CoWoS interposer and 5nm production lines at full capacity. Yesterday, we found out that AMD and Nvidia bought up all of their excess capacity for next-generation GPU and CPU development. They have also been making advancements in 3nm process development, but have not been able to put much work in because many of the tools necessary are currently unavailable or hard to find due to the COVID-19 pandemic. 3nm is already a lot of work as it is, but in a recent shareholders meeting, DigiTimes was able to figure out that TSMC is already planning to start the development of the 2nm Lithographic process.
TSMC's "3nm" node has reportedly been delayed by 6 months due to the pandemic. Samsung is facing similar delays on their own "3nm" node.
TSMC's "5nm" production has not been delayed, and AMD will reportedly use an exclusive enhanced "5nm" node for Zen 4 CPUs in 2021.
Previously: TSMC's Chip-on-Wafer-on-Substrate (CoWoS) Connects Multiple Interposers
High Demand Reported for TSMC's Chip-on-Wafer-on-Substrate Packaging
(Score: 3, Informative) by takyon on Saturday April 25 2020, @11:45PM
Ok, so changes happen to transistor designs on the new nodes to make them work. FinFET, GAAFET, etc. TSMC has had a pretty good track record [anandtech.com] (see table) of each node reducing power consumption at the same clock speed. Looks like 87.2% reduction from "20SOC" to "5FF".
For the hypothetical of shrinking the 486, you would have to make changes to get it on "5nm" or "3nm".
AMD and many other chip designers are fabless. They can sign a contract with TSMC, Samsung, GlobalFoundries, or even Intel, and hopefully companies like SkyWater soon (monolithic 3D at larger nodes). If there weren't any improved nodes available, they would just sit on the same node but take advantage of improved yields and better binning, or make bigger changes to the architecture.
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