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posted by martyb on Friday June 05 2020, @08:40AM   Printer-friendly
from the help-less,-please dept.

Linus Torvalds rejects 'beyond stupid' AWS-made Linux patch for Intel CPU Snoop attack

Linux kernel head Linus Torvalds has trashed a patch from Amazon Web Services (AWS) engineers that was aimed at mitigating the Snoop attack on Intel CPUs discovered by an AWS engineer earlier this year. [...] AWS engineer Pawel Wieczorkiewicz discovered a way to leak data from an Intel CPU's memory via its L1D cache, which sits in CPU cores, through 'bus snooping' – the cache updating operation that happens when data is modified in L1D.

In the wake of the disclosure, AWS engineer Balbir Singh proposed a patch for the Linux kernel for applications to be able to opt in to flush the L1D cache when a task is switched out. [...] The feature would allow applications on an opt-in basis to call prctl(2) to flush the L1D cache for a task once it leaves the CPU, assuming the hardware supports it.

But, as spotted by Phoronix, Torvalds believes the patch will allow applications that opt in to the patch to degrade CPU performance for other applications.

"Because it looks to me like this basically exports cache flushing instructions to user space, and gives processes a way to just say 'slow down anybody else I schedule with too'," wrote Torvalds yesterday. "In other words, from what I can tell, this takes the crazy 'Intel ships buggy CPU's and it causes problems for virtualization' code (which I didn't much care about), and turns it into 'anybody can opt in to this disease, and now it affects even people and CPU's that don't need it and configurations where it's completely pointless'."

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  • (Score: 0) by Anonymous Coward on Friday June 05 2020, @07:37PM

    by Anonymous Coward on Friday June 05 2020, @07:37PM (#1003919)

    It wasn't the RISC part of "relying on compiler optimizations" that made the Itanic sink, it was the EPIC part. You know, the part where Intel said "I'll see your reduced instruction set, and I'll raise you a VLIW", thereby turning the what-was-supposed-to-be-reduced-and-simple into a giant hellhole of NOPs because there's only so much parallellism you can extract from everyday, low-level code (which is what everyone is still writing, isn't it?).

    Many compilers already had trouble filling MIPS' delayed-branch slot, what was Intel smoking when they decided "it should be a no-brainer for a compiler to always issue three instructions between an assignment to a variable and its use, or between a computation and writing the result of that computation to memory. Oh, and you can't have any branches in between"?