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posted by martyb on Friday August 14 2020, @08:48PM   Printer-friendly
from the the-die-is-cast^W-stacked dept.

Samsung Announces "X-Cube" 3D TSV SRAM-Logic Die Stacking Technology

Yesterday, Samsung Electronics had announced a new 3D IC packaging technology called eXtended-Cube, or "X-Cube", allowing chip-stacking of SRAM dies on top of a base logic die through TSVs.

Current TSV deployments in the industry mostly come in the form of stacking memory dies on top of a memory controller die in high-bandwidth-memory (HBM) modules that are then integrated with more complex packaging technologies, such as silicon interposers, which we see in today's high-end GPUs and FPGAs, or through other complex packaging such as Intel's EMIB.

Samsung's X-Cube is quite different to these existing technologies in that it does away with intermediary interposers or silicon bridges, and directly connects a stacked chip on top of the primary logic die of a design.

Samsung has built a 7nm EUV test chip using this methodology by integrating an SRAM die on top of a logic die. The logic die is designed with TSV pillars which then connect to µ-bumps with only 30µm pitch, allowing the SRAM-die to be directly connected to the main die without intermediary mediums. The company this is the industry's first such design with an advanced process node technology.

[...] Stacking more valuable SRAM instead of DRAM on top of the logic chip would likely represent a higher value proposition and return-on-investment to chip designers, as this would allow smaller die footprints for the base logic dies, with larger SRAM cache structures being able to reside on the stacked die. Such a large SRAM die would naturally also allow for significantly more SRAM that would allow for higher performance and lower power usage for a chip.

3D SRAM is not a new idea, but this kind of stacking could become commonplace in CPUs within a few years. SRAM takes up a large amount of CPU die area, so stacking it into layers above or near cores could be beneficial.

Also at The Register and Guru3D.

Related: Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration
AMD Plans to Stack DRAM and SRAM on Top of its Future Processors


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  • (Score: 4, Interesting) by looorg on Friday August 14 2020, @10:37PM (3 children)

    by looorg (578) on Friday August 14 2020, @10:37PM (#1036801)

    So instead of a large surface area CPU will get once that is more like a cube? The heatsinks are going to have to look very interesting, sort of like a heatcage or are is this liquid cooling only?

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  • (Score: 3, Interesting) by takyon on Friday August 14 2020, @11:45PM (1 child)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Friday August 14 2020, @11:45PM (#1036824) Journal

    It's difficult to say. We should know more about how it works after their Hot Chips presentation next week.

    This isn't the only way SRAM could be stacked. Instead of smothering the whole CPU with it, maybe the SRAM portion of the die could be layered up, and the base of it would still be adjacent to the CPU cores.

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    • (Score: 2) by looorg on Saturday August 15 2020, @04:33PM

      by looorg (578) on Saturday August 15 2020, @04:33PM (#1037130)

      I guess they could once again split the two so that CPU is CPU and Memory is something outside and not integrated into it.

  • (Score: 2) by takyon on Friday August 21 2020, @12:02AM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Friday August 21 2020, @12:02AM (#1039613) Journal

    I don't see any further coverage of it and the Samsung Hot Chips thing is listed as a "poster" [wikipedia.org]. Not sure what that means given that they went streaming only.

    https://www.hotchips.org/program/ [hotchips.org]
    http://archive.is/bZQKW [archive.is]

    So I guess that's it for now. If the technology sucks and can't be cooled effectively, it won't gain traction.

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