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posted by Fnord666 on Saturday August 29 2020, @02:08AM   Printer-friendly
from the smaller-and-smaller dept.

Taiwan Semiconductor Manufacturing Company (TSMC) announced a number of node scaling details and technological advancements at its 2020 Technology Symposium:

TSMC's first "5nm" node (N5) has a lower defect rate than its initial "7nm" node did at the same point in its development cycle (high volume manufacturing, which N5 is now in). This is due in part to increasing use of extreme ultraviolet lithography (EUV). "5nm" will represent 11% of TSMC's sub-"16nm" wafer production in 2020.

TSMC's "3nm" node (N3) will continue to use FinFETs rather than gate-all-around (GAA) transistors, and is scheduled for volume production in mid-late 2022. Performance is expected to improve 10-15% at the same power (compared to N5), or power consumption will be reduced 25-30% for the same performance. Logic area density improvement will be 1.7x, but SRAM density will only increase by 1.2x, leading to a 1.27x overall density increase for chips that are 70% SRAM and 30% logic.

Intel's EMIB (Embedded Die Interconnect Bridge) connects "chiplets" together without using a full silicon interposer. TSMC has its own version that it is calling Local Si Interconnect (LSI), and it will be combined with other packaging technologies. TSMC has demonstrated 12-layer stacking of chips using through silicon vias (TSVs), although cooling or doing anything useful with them could be somebody else's job.

See also: TSMC Updates on Node Availability Beyond Logic: Analog, HV, Sensors, RF
TSMC Launches New N12e Process: FinFET at 0.4V for IoT
2023 Interposers: TSMC Hints at 3400mm2 + 12x HBM in one Package
TSMC and Graphcore Prepare for AI Acceleration on 3nm
TSMC Has Reportedly Secured Orders for Its 2nm Node – Samsung May Not Beat Its Foundry Rival Until 2030, Claims New Report


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  • (Score: 2) by Booga1 on Sunday August 30 2020, @09:20AM (1 child)

    by Booga1 (6333) on Sunday August 30 2020, @09:20AM (#1044121)

    Even with the names being inaccurate, I seem to recall Texas Instruments or another company claiming it was going to be extremely difficult, if not near impossible to go much below 130nm. That prediction didn't hold up well at all.

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  • (Score: 3, Interesting) by takyon on Monday August 31 2020, @11:13PM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Monday August 31 2020, @11:13PM (#1044740) Journal

    You can get the scoop on semiengineering.com [semiengineering.com].

    New Architectures, Much Faster Chips [semiengineering.com]
    5/3nm Wars Begin [semiengineering.com]
    Making Chips At 3nm And Beyond [semiengineering.com]
    Big Trouble At 3nm [semiengineering.com]
    Transistor Options Beyond 3nm [semiengineering.com]
    Why Scaling Must Continue [semiengineering.com]

    Working EUV is making the smaller nodes more viable, but it needs another round of improvements [semiengineering.com] within about 2 years. New transistors and materials are needed. FinFETs will be replaced with GAAFETs soon, and carbon nanotubes could make an appearance after that. Meaningful node scaling will run out and then the name of the game is 3D.

    Intel has it all figured out down to fakename "1.4nm". They will probably get there, but in what form and at what cost? I think monolithic 3D will rise before literal atomic limits can be reached. It will leave node scaling gains in the dust and improve performance by 2-4 orders of magnitude.

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