Stories
Slash Boxes
Comments

SoylentNews is people

SoylentNews is powered by your submissions, so send in your scoop. Only 17 submissions in the queue.
posted by martyb on Wednesday October 21 2020, @04:36AM   Printer-friendly
from the keeping-your-electrons-correlated dept.

Arm Spinout Reveals Correlated-Electron Memory Plans

Earlier this month, a group of eight Arm Research engineers established a startup, Cerfe Labs, to commercialize an experimental memory technology they had been working on for the past five years with Austin-based Symetrix. The technology, called correlated electron RAM (CeRAM), could become a nonvolatile replacement for the fast-access embedded SRAM used in processor high-level cache memory today. Besides being able to hold data in the absence of a power supply, which SRAM cannot do, CeRAM is likely to be considerably smaller than SRAM, potentially easing IC area issues as the industry's ability to keep shrinking transistors reaches its end.

[...] The device itself is just the correlated electron material sandwiched between two electrodes, similar in structure to resistive RAM, phase change RAM, and magnetic RAM but less complex than the latter. And like those three, it is constructed in the metal interconnect layers above the silicon, requiring only one transistor in the silicon layer to access it, as opposed to SRAM's six. [Cerfe Labs' CTO Greg Yeric] says the company has made devices that fit with 7-nanometer CMOS processes and they should be scalable in both size and voltage to 5-nanometers (today's cutting edge).

But it's CeRAM's speed that could make it a good replacement for SRAM. To date, they've made CeRAM with a 2-nanosecond pulse width for writing data, which is on par with what's needed for a processor's L3 cache; Yeric says they expect this speed to improve with development.

The carbon-doped nickel oxide material also has properties that are well beyond what today's nonvolatile memory can do, but they are not as completely proven. For example, CerLab has shown that the device works at temperatures as low as 1.5 kelvins—well beyond what any nonvolatile memory can do, and in range for a role in quantum computing control circuits. In the other direction, they've demonstrated device operation up to 125 °C and showed that it retains its bits at up to 400 °C. But these figures were limited by the equipment the company had available. What's more, the device's theory of operation suggests that CeRAM should be naturally resistant to ionizing radiation and magnetic field disturbances.


Original Submission

 
This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 2) by takyon on Wednesday October 21 2020, @01:17PM

    by takyon (881) <{takyon} {at} {soylentnews.org}> on Wednesday October 21 2020, @01:17PM (#1067144) Journal

    I don't know. What I do know is that SRAM scaling is becoming a big problem. Replacing it with something denser could lead to cheaper chips, higher core counts, etc.

    TSMC "5nm", "3nm", Stacked Silicon, and More [soylentnews.org]

    TSMC's "3nm" node (N3) will continue to use FinFETs rather than gate-all-around (GAA) transistors, and is scheduled for volume production in mid-late 2022. [...] Logic area density improvement will be 1.7x, but SRAM density will only increase by 1.2x, leading to a 1.27x overall density increase for chips that are 70% SRAM and 30% logic.

    3D TSV SRAM is another possible solution. Or CeRAM could get 3D stacked instead.

    --
    [SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
    Starting Score:    1  point
    Karma-Bonus Modifier   +1  

    Total Score:   2