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The Trillion-Transistor Chip That Just Left a Supercomputer in the Dust:
So, in a recent trial, researchers pitted the chip—which is housed in an all-in-one system about the size of a dorm room mini-fridge called the CS-1—against a supercomputer in a fluid dynamics simulation. Simulating the movement of fluids is a common supercomputer application useful for solving complex problems like weather forecasting and airplane wing design.
The trial was described in a preprint paper written by a team led by Cerebras's Michael James and NETL's Dirk Van Essendelft and presented at the supercomputing conference SC20 this week. The team said the CS-1 completed a simulation of combustion in a power plant roughly 200 times faster than it took the Joule 2.0 supercomputer to do a similar task.
The CS-1 was actually faster-than-real-time. As Cerebrus wrote in a blog post, "It can tell you what is going to happen in the future faster than the laws of physics produce the same result."
The researchers said the CS-1's performance couldn't be matched by any number of CPUs and GPUs. And CEO and cofounder Andrew Feldman told VentureBeat that would be true "no matter how large the supercomputer is." At a point, scaling a supercomputer like Joule no longer produces better results in this kind of problem. That's why Joule's simulation speed peaked at 16,384 cores, a fraction of its total 86,400 cores.
Previously:
Cerebras More than Doubles Core and Transistor Count with 2nd-Generation Wafer Scale Engine
Cerebras Systems' Wafer Scale Engine Deployed at Argonne National Labs
Cerebras "Wafer Scale Engine" Has 1.2 Trillion Transistors, 400,000 Cores
(Score: 4, Insightful) by Hartree on Monday November 23 2020, @06:19PM (13 children)
So, you're saying that a purpose built machine can beat out a general computer on a given problem.
This is hardly news. Google "Gravity Pipe" for a far older example.
(Score: 5, Insightful) by HiThere on Monday November 23 2020, @06:32PM (10 children)
IIUC, that's not what's happening. It's that really large scale integration allows faster intercommunication, and the problem has a limit as to how "embarrassingly parallel" it is. Neither is all that surprising, but manufacturing defects have limited the scale of integration. They still do, but the limit is higher.
OTOH, there's nothing that says this kind of chip will be profitable to produce.
Javascript is what you use to allow unknown third parties to run software you have no idea about on your computer.
(Score: 4, Insightful) by EvilSS on Monday November 23 2020, @07:20PM (6 children)
But, of course, we need to see more independent verification of their claims, and, as you suggest, their yield is the big "if" here. If they are tossing hundreds of wafers to get one working on, it would be a problem.
(Score: 3, Informative) by takyon on Monday November 23 2020, @08:13PM (2 children)
IIRC, it's built to be tolerant of defective cores. Maybe there's a controller or some other small part that must be in perfect shape for it to work, but it could mean that almost every wafer is usable, the complete opposite of tossing out hundreds to get one good one.
Another thing is that TSMC's "7nm" yield is very good in the first place. And it costs about $9,346 [techpowerup.com].
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(Score: 2) by HiThere on Monday November 23 2020, @10:43PM
Sounds promising, but that ordinary yield is based on assuming that only a small area of the surface needs to be free of defects. If they need too much error correction (or longer inter-processor routing) that, in and of itself, could slow things down a lot. There may well be only a few "grade A" chips, and a much larger number of grades B and C, which are slower, or have fewer working processors.
Javascript is what you use to allow unknown third parties to run software you have no idea about on your computer.
(Score: 2) by TheRaven on Tuesday November 24 2020, @11:20AM
Most modern CPUs are designed to be tolerant of defects to a degree. It's pretty easy if the defect is in the cache: you just disable part of the cache and sell the chip as a cheaper variant. Intel started doing this aggressively around the 486: if you had a defect in the FPU, it was sold as a 486SX, if it had a defect in the CPU, it was sold as a 487, if both passed tests then it was a 486DX. Around the Pentium 3 era, yields got high enough that they (and AMD) ended up selling higher-rated parts with lower model numbers, because that made more money that lowering the price of the high-end parts.
This kind of thing is *much* easier with a regular layout. If you design your network on chip correctly, you can just route around any units that didn't work. IBM and Sony did this with the Cell: most of the chips made had at a defect in one of the SPUs, these were put in Playstations with 7 SPUs. The ones with no defects were put in IBM server parts with 8 SPUs. The ones with a defect in the CPU were put on accelerator boards. If your 'chip' is a wafer full of cores in a regular layout with a NOC routing between them, you can power the whole thing up, test each core, and then configure your NOC switches to route around areas that don't work (including entire parts of the network if there's a fault in part of the network itself). The main difficulty is that each system you produce will have subtly different topology, which will affect inter-core latency and may impact overall performance. Oh, and powering / cooling a chip that big is also nontrivial...
sudo mod me up
(Score: 5, Interesting) by driverless on Monday November 23 2020, @10:34PM (2 children)
I was at the conference where this was introduced. The consensus among the attendees, all of whom were experts in the field, was that it was yet another attempt at WSI, was an impressive proof-of-concept, and like every other time this has been tried would sink without trace after a year or two. No-one could see where this was going or who would buy it apart from one or two national labs to play with it for awhile.
(Score: 0) by Anonymous Coward on Tuesday November 24 2020, @04:38PM (1 child)
Sorry... what is a "WSI," and why is this apparently not-a-big-deal? (I'm not as familiar with this field.)
(Score: 2) by takyon on Tuesday November 24 2020, @11:11PM
https://en.wikipedia.org/wiki/Wafer-scale_integration [wikipedia.org]
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(Score: 3, Interesting) by sjames on Monday November 23 2020, @08:05PM (2 children)
Exactly. Communications latency is the big killer of performance in a supercomputer. In anything but the most embarrassingly parallel computation, the communications latency will set an upper limit on the number of cores that can be usefully used in the computation.
CS-1's approach is obvious from a theoretical standpoint, it should surprise nobody that it is faster and more efficient from a theoretical standpoint. The problem has always been practicality.
As for cost, this approach will be specialty for quite a while and likely expensive due to terrible yields. It's simply hard to make a chip that large with no defects.
If this makes it to production, it's going to require an approach like the celeron or AMD's 3 core processors but at a larger scale. That is, each chip is likely to be a little different with disabled modules. That will add complexity. It's reletively easy to have 2 banks of cache and allow one to be disabled that it is to have 400,000 cores where some arbitrary number of them may be disabled. Programs intended for the platform will likely need to be configured for the particular chip they'll be run on. In spite of that, for some jobs it may be worth it.
(Score: 5, Informative) by takyon on Monday November 23 2020, @08:16PM (1 child)
https://www.anandtech.com/show/15838/cerebras-wafer-scale-engine-scores-a-sale-5m-buys-two-for-the-pittsburgh-supercomputing-center [anandtech.com]
It looks like the yield is nearly 100%. A % of defective cores are disabled on each chip.
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(Score: 2) by sjames on Monday November 23 2020, @10:28PM
Good info, thanks!
Looks like they did go with something like the Celeron Strategy here.
As pricy as it is, it may actually be cheaper than the alternative.
(Score: 3, Interesting) by BsAtHome on Monday November 23 2020, @06:35PM (1 child)
Only partially purpose built. You can better describe it with the operational method of a generic system for a subset of problems. It will do very well with many simulations. Maybe primarily related to fluid-dynamics problems, but that is not a limitation in many science problems. You can also build a nice ray-tracer ;-)
(Score: 2) by Hartree on Tuesday November 24 2020, @05:15AM
Yes, I should have read it deeper before answering. The big plus is the higher rate of communication between cores. That should help with more tightly coupled physical systems that don't bust up as well into largely independent elements. I'd be interested to see how well it works on something viciously that way and nonlinear like general relativity simulations.
On the other hand, the proof is in the profits. Gene Amdahl and Trilogy Systems crashed very hard in the early 80s when they tried wafer scale integration.