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The Trillion-Transistor Chip That Just Left a Supercomputer in the Dust:
So, in a recent trial, researchers pitted the chip—which is housed in an all-in-one system about the size of a dorm room mini-fridge called the CS-1—against a supercomputer in a fluid dynamics simulation. Simulating the movement of fluids is a common supercomputer application useful for solving complex problems like weather forecasting and airplane wing design.
The trial was described in a preprint paper written by a team led by Cerebras's Michael James and NETL's Dirk Van Essendelft and presented at the supercomputing conference SC20 this week. The team said the CS-1 completed a simulation of combustion in a power plant roughly 200 times faster than it took the Joule 2.0 supercomputer to do a similar task.
The CS-1 was actually faster-than-real-time. As Cerebrus wrote in a blog post, "It can tell you what is going to happen in the future faster than the laws of physics produce the same result."
The researchers said the CS-1's performance couldn't be matched by any number of CPUs and GPUs. And CEO and cofounder Andrew Feldman told VentureBeat that would be true "no matter how large the supercomputer is." At a point, scaling a supercomputer like Joule no longer produces better results in this kind of problem. That's why Joule's simulation speed peaked at 16,384 cores, a fraction of its total 86,400 cores.
Previously:
Cerebras More than Doubles Core and Transistor Count with 2nd-Generation Wafer Scale Engine
Cerebras Systems' Wafer Scale Engine Deployed at Argonne National Labs
Cerebras "Wafer Scale Engine" Has 1.2 Trillion Transistors, 400,000 Cores
(Score: 3, Informative) by takyon on Monday November 23 2020, @08:13PM (2 children)
IIRC, it's built to be tolerant of defective cores. Maybe there's a controller or some other small part that must be in perfect shape for it to work, but it could mean that almost every wafer is usable, the complete opposite of tossing out hundreds to get one good one.
Another thing is that TSMC's "7nm" yield is very good in the first place. And it costs about $9,346 [techpowerup.com].
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 2) by HiThere on Monday November 23 2020, @10:43PM
Sounds promising, but that ordinary yield is based on assuming that only a small area of the surface needs to be free of defects. If they need too much error correction (or longer inter-processor routing) that, in and of itself, could slow things down a lot. There may well be only a few "grade A" chips, and a much larger number of grades B and C, which are slower, or have fewer working processors.
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(Score: 2) by TheRaven on Tuesday November 24 2020, @11:20AM
Most modern CPUs are designed to be tolerant of defects to a degree. It's pretty easy if the defect is in the cache: you just disable part of the cache and sell the chip as a cheaper variant. Intel started doing this aggressively around the 486: if you had a defect in the FPU, it was sold as a 486SX, if it had a defect in the CPU, it was sold as a 487, if both passed tests then it was a 486DX. Around the Pentium 3 era, yields got high enough that they (and AMD) ended up selling higher-rated parts with lower model numbers, because that made more money that lowering the price of the high-end parts.
This kind of thing is *much* easier with a regular layout. If you design your network on chip correctly, you can just route around any units that didn't work. IBM and Sony did this with the Cell: most of the chips made had at a defect in one of the SPUs, these were put in Playstations with 7 SPUs. The ones with no defects were put in IBM server parts with 8 SPUs. The ones with a defect in the CPU were put on accelerator boards. If your 'chip' is a wafer full of cores in a regular layout with a NOC routing between them, you can power the whole thing up, test each core, and then configure your NOC switches to route around areas that don't work (including entire parts of the network if there's a fault in part of the network itself). The main difficulty is that each system you produce will have subtly different topology, which will affect inter-core latency and may impact overall performance. Oh, and powering / cooling a chip that big is also nontrivial...
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