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Phytium presents D2000 ARM-based octa-core desktop CPU for the Chinese market
The new Phytium D2000 processors use the same custom 64-bit ARMv8-compatible FTC663 cores integrated in last year's FeiTeng-2000/4 model, except now there are 4x 2-core clusters instead of 2. Each of these clusters shares a unified 2 MB L2 cache and 1 MB L3 cache (8 MB of L2 cache and 4 MB L3 cache in total). This architecture features a four-issue out-of-order pipeline combined with Phytium's latest dynamic branch predictor and INT / FP units supporting ARM's ASIMD instructions. There is also support for SM2 / SM3 / SM4 / SM9 cryptography algorithms and the proprietary PSPA 1.0 security platform.
As far as hardware specs go, the D2000 is not really a match for the latest Intel and AMD chips, as it is built on China's own 14 nm nodes. Still, it features all the standard features you would expect from an entry-level CPU, including 128-bit DDR4-3200 / LPDDR4 RAM support, 34 PCIe 3.0 lanes that can be split into four PCIe 3.0 x8 slots and two PCIe 3.0 x1 slots, plus 2x GbE NiCs, 32 GPIO lanes, and an integrated audio codec. There is no iGPU, however. Core clock speeds will be set between 2.3 - 2.6 GHz, with a 25 W TDP, and the processor scores 97.45 points in the SPECint test.
Phytium is currently rolling out the D2000 chips to Chinese PC OEMs, and the first systems featuring the new processors are expected to hit the market in late Q1 2021.
Many more details at Tom's Hardware.
(Score: 4, Interesting) by Anonymous Coward on Sunday January 10 2021, @04:56AM
Which unfortunately looks stillborn now. The last update was from 2017 or 2018 and they were expecting the patents for moving from SH2 to SH3/4 to expire in 2020 and 2022 or something. Problematicly, they were going to need to design a new 'SH5' for 64 bit extensions since the 64 bit version that had been build never got any real implementations and had a number of notable flaws in hindsight.
MIPS is still around and China's Loongson chips are based on an older ISA of it (May have updted since?) The latest MIPS ISAs broke ABI compatibility at least twice although I think a qemu executable shim can make legacy binaries work, at a performance penalty.
Besides that I honest think the best bet is waiting for the x86_64 patents to expire next year(?) find any other IP issues with implementing the ISA from either Intel or AMD, then work on standardizing a new socket, perhaps giving up the performance of integrated memory controllers and going back to a northbridge, only with better prefetch behavior on the cpu to cover up the memory latency, allowing any capacity of memory without reliance on the cpu's integrated memory controller.
By 2026 we'll have virtualization extensions, and if we fix the speculative execution flaws in a fork of the x86_64 architecture, we could both provide legacy x86 support in a same-chip solution, and have hardware that could be drop in compatible with future motherboard designs with all high performance technology. By doing this we could provide replacement legacy hardware (IE for industrial systems where drivers only run a specific OS version/speeds) and provide newer systems and busses that can interface with previous/alternative iterations of chips, much like Socket 7 and then Super Socket 7 allowed back in the 90s.