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posted by martyb on Monday March 15 2021, @11:06PM   Printer-friendly

AMD Unveils EPYC 'Milan' 7003 CPUs, Zen 3 Comes to 64-Core Server Chips

AMD unveiled its EPYC 7003 'Milan' processors today, claiming that the chips, which bring the company's powerful Zen 3 architecture to the server market for the first time, take the lead as the world's fastest server processor with its flagship 64-core 128-thread EPYC 7763. Like the rest of the Milan lineup, this chip comes fabbed on the 7nm process and is drop-in compatible with existing servers. AMD claims it brings up to twice the performance of Intel's competing Xeon Cascade Lake Refresh chips in HPC, Cloud, and enterprise workloads, all while offering a vastly better price-to-performance ratio.

Milan's agility lies in the Zen 3 architecture and its chiplet-based design. This microarchitecture brings many of the same benefits that we've seen with AMD's Ryzen 5000 series chips that dominate the desktop PC market, like a 19% increase in IPC and a larger unified L3 cache. Those attributes, among others, help improve AMD's standing against Intel's venerable Xeon lineup in key areas, like single-threaded work, and offer a more refined performance profile across a broader spate of applications.

One interesting new SKU is the EPYC 7663, a 56-core, 112-thread CPU with 7 working cores on each of the 8-core chiplets. There is also a 28-core EPYC 7453.

Next up, Zen 4 "Genoa".

Also at AnandTech, The Next Platform, Phoronix, and Ars Technica.

See also: The Tour of Italy with EPYC Milan: Interview with AMD's Forrest Norrod
AMD video announcement (51m4s) and recap (10m43s)


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  • (Score: 2) by takyon on Tuesday March 16 2021, @09:38AM

    by takyon (881) <takyonNO@SPAMsoylentnews.org> on Tuesday March 16 2021, @09:38AM (#1124771) Journal

    I think the move to the unified 8-core core complex (CCX) is what makes the 7-core chiplet possible, or at least make more sense. They didn't want irregular amounts of cores on Zen 2 CCXs, or it was not possible to disable a core on a CCX without disabling a core on the other one. Each of the 7 cores can access the full 32 MB of L3 cache.

    TSMC "7nm" was already mature to the point that many perfectly good 8-core chiplets have been neutered into 6-cores. There is already slight variance in performance of chips due to the silicon lottery, so a chiplet used for a 6-core might be tolerated in an 8-core.

    Zen 4 is going to be one to watch for the binning. It's assumed that it will increase core counts by 50% on at least some product lines (no "mainstream" 24-core would be a disappointment). They can do that by adding more 8-core chiplets or switching to a 12-core chiplet. A recent leak points to 8-core chiplets [notebookcheck.net] again, but 12-core would probably be better for consumers since it could force 6-core out of the picture, improve latency across 12 cores on a single chiplet (for workloads or games that can use 12 cores), enable a cheap single chiplet 10-core, etc.

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