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AMD patents a task transition method between BIG and LITTLE processors
The next decade will no longer be dictated by the number of cores, but rather the processor's fabrication node, packaging method, and power efficiency. A big role will also be played by heterogeneous architectures.
Later this year Intel will launch its 12th Gen Core Alder Lake processors for desktop and mobile systems. This is not the first architecture to implement Intel's Hybrid Technology (the first was Lakefield). This is a marketing term for high-efficiency (small) and high-performance (big) core implementation. Most tech users should be more familiar with the term big.LITTLE, which is actually an old name for ARM's heterogeneous computing architecture, now replaced by DynamIQ.
While heterogeneous CPUs have been used in mobile devices for years, this technology isn't exactly a domain of modern desktop PCs, where power efficiency is not exactly the biggest concern. The next-generation Windows operating system is rumored to feature a new task scheduling method for such heterogeneous computing, which might just align with Intel's Alder Lake launch.
While AMD has not really confirmed it is working on such [a] processor design, the leaks have brought us a new codename 'Strix Point', which is associated with [a] Zen5 based APU, supposedly also featuring smaller cores known as Zen4D. The latter is a codename of the smaller core.
Just two days ago, an AMD patent on 'task transition between heterogeneous processors' has been published. This patent was originally filed in December 2019, which suggests AMD has clearly been working on this technology for a long time. The patent covers the most important engineering problem of heterogeneous computing, which is how to schedule or transition tasks between different types of cores.
It looks like both Intel and AMD will adopt heterogeneous x86 microarchitectures in future desktop and mobile processors. Smaller cores can deliver better performance-per-Watt and performance-per-mm2 of die area, allowing for greater potential gains in multi-threaded performance, while big cores deliver better single-thread performance.
Intel's Alder Lake desktop CPUs will have up to 8 big and 8 small cores, and are expected to be announced or launched around October 25. It will support both DDR4 and DDR5 memory depending on the motherboard used. Intel is rumored to follow that up with Raptor Lake CPUs in 2022 featuring 8 big and 16 small cores.
The rumored AMD Strix Point APUs could launch as late as 2024, with a mix of Zen 5 (big) and "Zen 4D" (small) cores on TSMC's "3nm" process.
Also at Tom's Hardware.
Previously: Intel Architecture Day 2020: Tiger Lake, Alder Lake, Discrete GPUs, and More
(Score: 2) by takyon on Monday June 14 2021, @06:30PM
If an application is multi-threaded but can only use a limited number of cores, then it's better to have those cores be as fast as possible. Both the Xbox Series X/S and PS5 have 8 "big" Zen 2 cores with support for 2 threads per core, so that will become the minimum standard for gaming for about a decade. You can expect utilization of that many cores (maybe less), but shouldn't expect huge benefits beyond that. However, it has been argued that you want even more cores to do the job of dedicated hardware in the consoles, and maybe the small cores can handle some of that:
https://www.eurogamer.net/articles/digitalfoundry-2020-playstation-5-specs-and-tech-that-deliver-sonys-next-gen-vision [eurogamer.net]
Other applications can probably benefit from having 2-4 big cores since that has been the standard for a long time now. A web browser can obviously use more than 1 big core, but I don't think you would get much benefit from an absurd number of cores, like 64.
For anything that can scale to as many cores as you can throw at it, like a compiler, video encoder, Blender, etc., you would like to have as many big cores as possible, but a greater number of small cores would also be acceptable and more cost-efficient. Which is why we will see 8+8 become 8+16.
Alder Lake is replacing Comet Lake which had up to 10 big cores, and Rocket Lake which had to be dropped back down to 8.
Intel's "beta test" of hybrid x86 was Lakefield, a low TDP chip with 1 big and 4 small cores. Intel is still launching desktop chips with small Atom cores, such as Jasper Lake [wikipedia.org]. Future low TDP lineups should definitely move towards configurations like 1+8, because it would simply be faster than it was previously when limited to only Atom cores. Mobile chips could also use configurations like that, but we will see 6+8 and even the full 8+8 crammed into gaming laptops.
On the ARM side, we are seeing huge/big/small, e.g. 1x Cortex-X1, 3x Cortex-A78, 4x Cortex-A55. It could be a long time before we see any SoCs with more than one Cortex-Xn core. The Cortex-X1 is similar but physically larger than the Cortex-A78, usually has more cache, etc.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]