SoylentNews is people
SoylentNews
Imagination Technologies to design RISC-V cores:
Now better known for its PowerVR embedded GPUs, Imagination Technologies tried to enter the CPU market by purchasing MIPS Technologies and introducing microAptiv, interAptiv, and proAptiv cores in 2012.
It did not end up well, as the company had to sell its MIPS technology a few years later, and the MIPS architecture is now barely supported. But Imagination is now working on getting back into the CPU space by designing RISC-V cores.
[...] a May 2021 report by the Financial Times claims Imagination expects to invest up to $150m over the next two years to target a fresh push into the processor design market, specifically citing the RISC-V architecture.
Also at Tom's Hardware.
See also: QEMU 6.1 Released With RISC-V Improvements, AMD Emulation Fixes
Related: Imagination Technologies Acquired for $675 Million, MIPS to be Sold Off
Wave Computing Acquires MIPS Technologies
Imagination Announces B-Series GPU IP: Scaling up with Multi-GPU
(Score: 4, Interesting) by Snotnose on Friday August 27 2021, @09:31PM (3 children)
Back around 2000 my job was to certify CPUs for Microsoft. I don't remember the exact details, but Microsoft had a set of code I could minimally change to prove a CPU could run Microsoft code.
x86? Never saw it
SH-4? Minor issues but not a big deal.
MIPS? If memory serves they reserved the upper 25% of memory for I/O. In other words, if you went above 0xd000000000 (I hope I got that right) then you were doing I/O, not memory. The Microsoft test wanted 100% of the 32 bit memory space to be memory.
I contacted the Microsoft guy who wrote the tests, his attitude was pretty much "thems the specs, deal". I couldn't deal, I had no say on the hardware. The hardware wasn't going to pass, the hardware vendor wanted it to pass, Microsoft was pretty much "tell him I'm at lunch".
Keep in mind back in 2000 Microsoft was approving CPUs for WinCe, which is the most accidentally appropriate name for an OS I've ever run across. Back then having a full 32 bit addressing space for an embedded system was not going to happen. Plus, WinCE. A horrible RTOS that showed Microsoft had no clue what a RTOS was. Where do I start?
1) How much stack space does each process need? Dunno.
2) What is the Interrupt latency? Dunno
3) How much RAM does each process need? Dunno
4) When will process X get to run? Dunno
In other words, calling WinCE an RTOS was a joke. And as it turned out, reserving 25% of your addressing space for I/O also turned out to be a fail. But, somehow, I got the MIPS approved. I don't remember how, I just remember WinCE as a huge joke.
Relationship status: Available for curbside pickup.
(Score: 0) by Anonymous Coward on Friday August 27 2021, @09:51PM
0xc0000000-0xffffffff is the top 1/4 of 32 bit memory. This range is often reserved for the OS on x86-32 so reserving it for I/O would conflict. Maybe they moved to a high-half design and blocked out 0x80000000-0xbfffffff for the OS?
(Score: 4, Funny) by Tork on Friday August 27 2021, @10:06PM
I respectfully disagree. I've had a few WinCE devices and I can tell you it wasn't like it was smooth sailing and then you'd hit a wall, all the wincing happened in real-time.
Slashdolt Logic: "25 year old jokes about sharks and lasers are +5, Funny." 💩
(Score: 2) by shortscreen on Saturday August 28 2021, @01:25AM
x86 systems (post-PCI anyway) use the latter part of the physical address space for I/O. 0xD0000000 is often used as a window to access memory on the video card. (Remember setting the AGP aperture size in the old BIOS setup?) Other PCI devices take chunks of address space up there too. That's why 32-bit Windows would top out at 3.25GB or so.
I don't know anything about MIPS but are you sure they reserved 25% for I/O? This page says only the last 64KB http://www.cs.uwm.edu/classes/cs315/Bacon/Lecture/HTML/ch14s03.html [uwm.edu]