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takyon writes:

Chip world veterans gather to design customizable, chiplet-based RISC-V server chips

A Silicon Valley startup is stepping out of stealth mode today, publicly vowing to supply high-performance data-center-class RISC-V processors.

Ventana Micro Systems said since its founding in 2018 it has secured $53m in funding in series A and B rounds, the latter of which totaled $38m and was led by Marvell founders Sehat Sutardja and Weili Dai.

It is hoped the first samples of its 64-bit RISC-V processors will be shared with customers in the second half of next year, and ship in volume in the first half of 2023. It's worth remembering that big biz rarely significantly commits to using someone's silicon until it reaches second generation; the first generation is mostly for evaluation of the platform, which is where Ventana is at right now.

The processors, CEO and cofounder Balaji Baktha explained to us, will use a chiplet approach, as seen with AMD and lately Intel. That is to say, each chip will contain a number of discrete dies – some with CPU cores, some with custom acceleration, and others with IO and memory interfaces – interconnected within a single package.

[...] Ventana's compute dies each feature 16 RISC-V cores. Baktha said these out-of-order, four-wide superscalar cores should outperform RV64 rivals and at least match Arm's Neoverse data-center-class CPUs.

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