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posted by janrinok on Tuesday December 14 2021, @04:04PM   Printer-friendly

New IBM and Samsung transistors could be key to super-efficient chips (updated)

IBM and Samsung claim they've made a breakthrough in semiconductor design. On day one of the IEDM [(International Electron Devices Meeting)] conference in San Francisco, the two companies unveiled a new design for stacking transistors vertically on a chip. With current processors and SoCs, transistors lie flat on the surface of the silicon, and then electric current flows from side-to-side. By contrast, Vertical Transport Field Effect Transistors (VTFET) sit perpendicular to one another and current flows vertically.

According to IBM and Samsung, this design has two advantages. First, it will allow them to bypass many performance limitations to extend Moore's Law beyond IBM's current nanosheet technology. More importantly, the design leads to less wasted energy thanks to greater current flow. They estimate VTFET will lead to processors that are either twice as fast or use 85 percent less power than chips designed with FinFET transistors. IBM and Samsung claim the process may one day allow for phones that go a full week on a single charge. They say it could also make certain energy-intensive tasks, including cryptomining, more power-efficient and therefore less impactful on the environment.

IBM blog post. Also at Notebookcheck.

See also: Samsung Begins Sampling 24 Gbps GDDR6 Memory Chips For Next-Gen GPUs


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  • (Score: 3, Interesting) by mcgrew on Tuesday December 14 2021, @07:46PM (5 children)

    by mcgrew (701) <publish@mcgrewbooks.com> on Tuesday December 14 2021, @07:46PM (#1205065) Homepage Journal

    They finally did it? I remember reading about the studies over twenty years ago.

    The second paragraph is kind of common sense. Picture printed circuit boards stacked, with some wires in the center going through holes in the middle of the stack to reach the top, and every other permutation. The farther current has to go to more the conductor heats (energy loss) and the longer it takes for the signal to get there.

    For an amusing picture, imagine a circuit board big enough to hold all of the billions of discrete components in a CPU or memory chip, not just transistors. Bigger than the land area of a city? Haven't bothered to do the math.

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    mcgrewbooks.com mcgrew.info nooze.org
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  • (Score: 3, Funny) by EvilSS on Tuesday December 14 2021, @09:39PM (2 children)

    by EvilSS (1456) Subscriber Badge on Tuesday December 14 2021, @09:39PM (#1205119)
    Now if they could just get the Beryllium Oxide Based Active Field Effect Transistors out of the lab and into production.
    • (Score: 0) by Anonymous Coward on Tuesday December 14 2021, @11:04PM

      by Anonymous Coward on Tuesday December 14 2021, @11:04PM (#1205141)

      The problem with those, however, is that you're not supposed to take them out of their packaging because it ruins their value.

    • (Score: 2) by mcgrew on Saturday December 18 2021, @08:53PM

      by mcgrew (701) <publish@mcgrewbooks.com> on Saturday December 18 2021, @08:53PM (#1206213) Homepage Journal

      Whenever I see the word "Beryllium" I think of an Asimov story called Sucker Bait. It has a character who is obviously autistic even though it was decades before autism was ever recognized.

      --
      mcgrewbooks.com mcgrew.info nooze.org
  • (Score: 2) by ChrisMaple on Thursday December 16 2021, @06:37AM (1 child)

    by ChrisMaple (6964) on Thursday December 16 2021, @06:37AM (#1205506)

    My understanding of this (I could easily be wrong) is that the performance gain is made possible by having extremely short gates. Gate length is the primary speed limitation in digital FET IC tech, not conductor losses. Vertical FETs have the gate length set by layer thickness, which can almost be controlled in units of atoms. By way of contrast, horizontal FET gate length is controlled by lithography, which is much less accurate.