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posted by janrinok on Tuesday December 14 2021, @04:04PM   Printer-friendly

New IBM and Samsung transistors could be key to super-efficient chips (updated)

IBM and Samsung claim they've made a breakthrough in semiconductor design. On day one of the IEDM [(International Electron Devices Meeting)] conference in San Francisco, the two companies unveiled a new design for stacking transistors vertically on a chip. With current processors and SoCs, transistors lie flat on the surface of the silicon, and then electric current flows from side-to-side. By contrast, Vertical Transport Field Effect Transistors (VTFET) sit perpendicular to one another and current flows vertically.

According to IBM and Samsung, this design has two advantages. First, it will allow them to bypass many performance limitations to extend Moore's Law beyond IBM's current nanosheet technology. More importantly, the design leads to less wasted energy thanks to greater current flow. They estimate VTFET will lead to processors that are either twice as fast or use 85 percent less power than chips designed with FinFET transistors. IBM and Samsung claim the process may one day allow for phones that go a full week on a single charge. They say it could also make certain energy-intensive tasks, including cryptomining, more power-efficient and therefore less impactful on the environment.

IBM blog post. Also at Notebookcheck.

See also: Samsung Begins Sampling 24 Gbps GDDR6 Memory Chips For Next-Gen GPUs

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  • (Score: 2) by ChrisMaple on Thursday December 16 2021, @06:58AM

    by ChrisMaple (6964) on Thursday December 16 2021, @06:58AM (#1205510)

    The summary surely makes it confusing.

    To a first approximation, losses in digital ICs are caused by the current flowing through equivalent resistances to charge up capacitances. Most of the capacitance is in the FET gate, and most of the resistance is in the FET channel. If the resistance of the channel is lower, the capacitance charges up faster and at a higher current, but the total energy consumed remains unchanged at 0.5*C*V^2. A trade-off that allows lower power is to make the vertical transistor's gate smaller so that it passes the same or less current as the equivalent horizontal transistor, but has much less capacitance. Less gate capacitance means less energy per transition.

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