SoylentNews is people
SoylentNews
SK Hynix to Manufacture 48 GiB and 96 GiB DDR5 Modules
Today SK Hynix is announcing the sampling of its next generation DDR5 memory. The headline is the commercialization of a new 24 gigabit die, offering 50% more capacity than the leading 16 gigabit dies currently used on high-capacity DDR5. Along with reportedly reducing power consumption by 25% by using SK Hynix's latest 1a nm process node and EUV technology, what fascinates me most is that we're going to get, for the first time in the PC space (to my knowledge), memory modules that are no longer powers of two.
For PC-based DDR memory, all the way back from DDR1 and prior, memory modules have been configured as a power of two in terms of storage. Whether that's 16 MiB to 256 MiB to 2 GiB to 32 GiB, I'm fairly certain that all of the memory modules that I've ever handled have been powers of two. The new announcement from SK Hynix showcases that the new 24 gigabit dies will allow the company to build DDR5 modules in capacities of 48 GiB and 96 GiB.
To be clear, the DDR5 official specification actually allows for capacities that are not direct powers of two. If we look to other types of memory, powers of two have been thrown out the window for a while, such as in smartphones. However PCs and Servers, as least the traditional ones, have followed the power of two mantra. One of the changes in memory design that is now driving regular modules to non-power of two capacities is that it is getting harder and harder to scale DRAM capacities. The time it takes to figure out the complexity of the technology to get a 2x improvement every time is too long, and memory vendors will start taking those intermediate steps to get product to market.
These are for server RDIMMs, at least for now.
Related: SK Hynix Begins Production of 18 GB LPDDR5 Memory... for Smartphones
Samsung Developing 24Gb DDR5 ICs: 768GB DDR5 Modules Possible
(Score: 2) by Mojibake Tengu on Thursday December 16 2021, @07:00PM (1 child)
Physical address space on AMD64 architecture is currently limited to 48 bits by ISA design, so memory manufacturers still have a plenty of space for improvement.
For CPU manufacturer, just adding more channels to Infinity Fabric would be trivial update.
The edge of 太玄 cannot be defined, for it is beyond every aspect of design
(Score: 0) by Anonymous Coward on Wednesday December 29 2021, @11:19AM
That was the last I heard Intel/AMD were doing and I think there was another plan to expand out to 54 bit, but it's starting to get into the flag bits they'd put on the high order bits of the address pointers.