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posted by janrinok on Friday May 20 2022, @09:56AM   Printer-friendly
from the dont-put-some-of-your-eggs-in-too-many-baskets dept.

Tech war: China bets on open-source RISC-V for chip design to minimise potential damage from 'being cut off' by US sanctions

A growing number of Chinese chip design firms have adopted open-source RISC-V in their chip designs as an alternative to Intel's proprietary X86 and Arm's architecture, in a bid to minimise potential damage from US sanctions and to save on licensing fees.

[....] "[This] gives Chinese companies access to a global open standard instruction set architecture (ISA) ecosystem," said Stewart Randall, head of electronics and embedded software at consultancy Intralink. "So Chinese companies can have access to, and create, their own cores or chips based on it."

However, some industry experts said China's adoption of open-source RISC-V architecture would not shield them from all US sanction risks, as America still holds the trump card when it comes to electronic design automation (EDA) tools, the key software needed for chip design, as well as chip manufacturing technologies.

If you really want to create your own cores from scratch, without licensing anyone else's IP, is it truly possible to do so with RISC-V?

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Tech war: China bets on open-source RISC-V for chip design to minimise potential damage from 'being cut off' by US sanctions


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  • (Score: 1, Informative) by Anonymous Coward on Friday May 20 2022, @12:02PM (2 children)

    by Anonymous Coward on Friday May 20 2022, @12:02PM (#1246546)

    Intel CPUs have been "RISC" for many years now. The CISC Intel instructions are translated into RISC instructions and run by a RISC core. To be totally precise, all modern CPUs are a hybrid of RISC and CISC, using design aspects of each that make sense. Thus, you could say modern CPUs are "mostly RISC."

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  • (Score: 0) by Anonymous Coward on Saturday May 21 2022, @08:21PM (1 child)

    by Anonymous Coward on Saturday May 21 2022, @08:21PM (#1246912)
    I heard one of the difficulties with speeding up Intel CISC instructions is that they're variable length.

    For example you can't assume that every instruction is 4 bytes so if you're going to speculatively execute 4 instructions you can't just simply fetch 4 sets of 4 bytes and try speculatively executing each instruction.

    That said ARM has the thumb instruction set too.
    • (Score: 0) by Anonymous Coward on Sunday May 22 2022, @05:38PM

      by Anonymous Coward on Sunday May 22 2022, @05:38PM (#1247058)

      this is a feeling, since i am no chip designer, but the CISC legacy of intel was prolly influenced by the biggest enabler *cough*m$*cough* which needed a cpu that was a "caset player" for windows software.
      so, like a win-cpu, not a fast, lean, smart cpu design where other OS software could make use of it.
      again, i have a feeling that cpu designers at intel sighed a breath of relief when linux came on to the scene and a chance to remove the cruft and add some risc?
      no linux happend, we'd prolly have >20 long CISC instruction sets gear for .NET intel chips.