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Intel and the Barcelona Supercomputing Centre (BSC) said they would invest €400 million (around $426 million) in a laboratory that will develop RISC-V-based processors that could be used to build zettascale supercomputers. However, the lab will not focus solely on CPUs for next-generation supercomputers but also on processor uses for artificial intelligence applications and autonomous vehicles.
The research laboratory will presumably be set up in Barcelona, Spain, and will receive €400 million from Intel and the Spanish Government over 10 years. The fundamental purpose of the joint research laboratory is to develop chips based on the open-source RISC-V instruction set architecture (ISA) that could be used for a wide range of applications, including AI accelerators, autonomous vehicles, and high-performance computing.
The creation of the joint laboratory does not automatically mean that Intel will use RISC-V-based CPUs developed in the lab for its first-generation zettascale supercomputing platform but rather indicates that the company is willing to make additional investments in RISC-V. After all, last year, Intel tried to buy SiFive, a leading developer of RISC-V CPUs and is among the top sponsors of RISC-V International, a non-profit organization supporting the ISA.
[....] throughout its history, Intel invested hundreds of millions in non-x86 architectures (including RISC-based i960/i860 designs in the 1980s, Arm in the 2000s, and VLIW-based IA64/Itanium in the 1990s and the 2000s). Eventually, those architectures were dropped, but technologies developed for them found their way into x86 offerings.
I would observe that a simple well designed instruction set could require less silicon. Possibly more cores per chip using same fabrication technology. Or more speculative execution branch prediction using up some of that silicon. I would mention compiler back ends, but that is a subject best not discussed in public.
(Score: 3, Insightful) by maxwell demon on Saturday June 04 2022, @04:39AM (4 children)
Intel already tried to do better than existing RISC chips. The result was called Itanium. Didn't work out too well.
The Tao of math: The numbers you can count are not the real numbers.
(Score: 2) by DannyB on Saturday June 04 2022, @04:57PM
Itanic was an ultra wide instruction word as I seem to recall. Multiple instructions per word.
Not what most people think of as RISC.
The lower I set my standards the more accomplishments I have.
(Score: 2) by stormwyrm on Saturday June 04 2022, @07:11PM (2 children)
Numquam ponenda est pluralitas sine necessitate.
(Score: 2) by turgid on Sunday June 05 2022, @08:48AM (1 child)
I believe the problem with the i860 [cpushack.com] was that it was too slow at context switching (it took too long to store and restore all the registers) so it wasn't much good as a general purpose CPU. It was very good for graphics, though, and had hardware support for some 3D stuff. It was on some graphics cards. There was an aborted attempt to port Windows NT to the i860.
The i960 was also RISC but a very different architecture. It was used for embedded stuff. Several laser printers had i960s in them.
Those were exciting days when all these new designs were coming out. There was quite a competitive market with RISC CPUs such as SPARC, MIPS, i860, M88k, POWER, PowerPC and all sorts of others, The mainstream was using the 386 and Motorola 680x0 series, which were much slower. When the DEC Alpha came out, it blew everything else clear out of the water.
I refuse to engage in a battle of wits with an unarmed opponent [wikipedia.org].
(Score: 0) by Anonymous Coward on Friday June 10 2022, @05:35AM
It was actually the architectural starting point for Windows NT, before NT was further ported to other architectures as planned, but having made no assumptions based on those architecture designs. You can find a reference to this in one of those microsoft blog posts (raymond chen, or somebody else?) regarding an interview with one of those early NT developers and using the cobbled together i860 system that didn't even have graphics when it was started (it was text only over a serial console!) The i60 work was completed when the got all the major kernel components completed and the HAL stuff finalized at which point the focus shifted to the intended architectures (ppc and x6 if I remember correctly) before eventually gaining alpha and mips, then contracting back to only x86 before eventually picking up arm.