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from the might-have-to-wait-for-a-Black-Friday-sale dept.
Arthur T Knackerbracket has processed the following story:
At advanced nodes, chips are not getting cheaper.
Apple's A-series smartphone processors have evolved significantly from the A7 (28nm) to the A18 Pro (3nm), gaining more cores, transistors, and features. With each new node, TSMC charged Apple more per wafer, so the price increased from $5,000 for a 28nm wafer with A7 processors to $18,000 for a 3nm-class wafer for A17 and A18-series processors, reports Ben Bajarin, the chief executive and principal analyst at Creative Strategies.
Bajarin notes that as Apple's A-series chips have evolved, their transistor count has consistently increased, starting at 1 billion in the A7 and reaching 20 billion in the A18 Pro. That makes sense because the number of cores and features has also increased: in 2013, the A7 featured two high-performance cores and a four-cluster GPU, whereas, in 2024, the A18 Pro features two high-performance cores, four energy-efficient cores, a 16-core NPU, and a six-cluster GPU.
Got a detailed price/die/density analysis of Apple A-silicon over time at TSMC. Some nuggets.From A7 to A18:- progression from 28nm to 3nm- Most dramatic shrinks occurred early (28nm → 20nm → 16nm/14nm)- Steady increase in transistor count from 1 billion (A7) to 20…December 18, 2024
A-series processors are aimed at smartphones, and Bajarin says their die sizes have remained relatively consistent, ranging between 80 and 125 square millimeters across generations. This was enabled by a steady increase in transistor densities facilitated by TSMC's latest process technologies.
The most substantial transistor density increases occurred in the earlier nodes, such as transitions from 28nm to 20nm and then to 16nm/14nm. However, recent process technologies (N5, N4P, N3B, N3E) exhibit slower density improvements. The peak period for transistor density improvements occurred around the A11 (N10, 10nm-class) and A12 (N7, 7nm-class), with gains of 86% and 69%, respectively. Recent chips, including the A16 to A18 Pro, show a noticeable slowdown in density advancements, primarily due to slower SRAM scaling.
However, despite diminishing returns, Bajarin notes that production costs have risen sharply. Wafer prices climbed from $5,000 for the A7 to $18,000 for the A17 and A18 Pro, while the cost per square millimeter increased from $0.07 to $0.25.
Bajarin says his information comes from a third-party supply chain report, and the company that produced it has sources at TSMC. Bajarin has also triangulated certain factors through his own sources. In general, the listed TSMC pricing looks more or less consistent with previous reports, though we should always take non-official information with a grain of salt.
To make things even harder for Apple, performance increases have also slowed down with the latest generations of its processors (with A18 and M4-series being exceptions) as it got harder to extract higher instruction per cycle (IPC) throughput with the latest architectures. Nonetheless, Apple has managed to maintain performance-per-watt gains with each generation.
"Given it is harder to pull out IPC gains, but getting efficiencies where they can even if its costs related to area increase, [is a viable] performance-per-watt [gain] strategy," Bajarin told Tom's Hardware.
According to well-cited industry reports, TSMC always sells its customers wafers with sellable and non-sellable dies, not just sellable dies. Therefore, the number of chips derived from a wafer depends on the manufacturing yield. Higher yields produce more chips per wafer, while lower yields result in fewer. This yield-based variability impacts the cost-effectiveness of the wafers for customers. However, there is one important part here: TSMC guarantees that it will try to achieve a certain yield target before production starts.
If the actual yield falls short by a substantial margin, such as 10% to 15%, TSMC may provide financial compensation or discounts to affected customers. These terms aim to reassure clients about TSMC's reliability and the value of their high-cost wafers.
Being an alpha customer for the latest process technologies, Apple has a chance to adjust manufacturing processes to lower defect density and increase its yields, so the company is in a better position from a cost perspective than other TSMC clients. Also, it's rumored that Apple is TSMC's only customer that pays TSMC on a per-chip, not per-wafer, basis. If true, this sets Apple further apart from other TSMC customers.
(Score: 3, Informative) by ChrisMaple on Saturday January 11, @05:52AM
Part of the wafer price increase is due to the dollar having lost a lot of its value. Another part is that advanced processes have more layers, and each added layer adds cost. Yet another part is that the fab equipment for smaller features is more expensive.
Nobody should be surprised that somebody who buys a wafer gets some defective dice. That's always been true; semiconductors have defects.
For semiconductors, the plural of die is dice. Not dies.
At first glance, denser processes would seem to allow smaller chips in inverse proportion to device density, without limit. However, bonding pads cannot be scaled as aggressively as devices, because bonding has different physical requirements. If there are 1,000 bonding pads on your CPU, that may set a minimum size for a die. If you take a processor that filled up all of the available space of a 28 nm process die inside the pad ring, and move that processor to a 3 nm process, the pad ring will still define the die size but the processor will be much smaller. Not using the newly available space is just wasteful, so features are added: multiple cores, more cache, specialized functions, etc..