Slash Boxes

SoylentNews is people

posted by janrinok on Thursday March 27 2014, @03:03AM   Printer-friendly
from the looking-forward-to-some-pretty-pictures dept.

pbnjoe writes:

Ars technica is reporting on new devlopments in GPU interconnect tech.

From the article:

Nvidia and IBM have developed an interconnect that will be integrated into future graphics processing units, letting GPUs and CPUs share data five times faster than they can now, Nvidia announced today. The fatter pipe will let data flow between the CPU and GPU at rates higher than 80GB per second, compared to 16GB per second today. NVLink, the interconnect, will be part of the newly announced Pascal GPU architecture on track for release in 2016.

GPUs have become increasingly common in supercomputing, serving as accelerators or "co-processors" to help CPUs get work done faster. In the most recent list of the world's fastest 500 supercomputers, 53 systems used co-processors and 38 of these used Nvidia chips. The second and sixth most powerful supercomputers used Nvidia chips alongside CPUs. Intel still dominates, providing processors for 82.4 percent of Top 500 systems.

"Today's GPUs are connected to x86-based CPUs through the PCI Express (PCIe) interface, which limits the GPU's ability to access the CPU memory system and is four- to five-times slower than typical CPU memory systems," Nvidia said. "PCIe is an even greater bottleneck between the GPU and IBM Power CPUs, which have more bandwidth than x86 CPUs. As the NVLink interface will match the bandwidth of typical CPU memory systems, it will enable GPUs to access CPU memory at its full bandwidth... Although future Nvidia GPUs will continue to support PCIe, NVLink technology will be used for connecting GPUs to NVLink-enabled CPUs as well as providing high-bandwidth connections directly between multiple GPUs.

This discussion has been archived. No new comments can be posted.
Display Options Threshold/Breakthrough Mark All as Read Mark All as Unread
The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
  • (Score: 3, Informative) by visaris on Thursday March 27 2014, @12:46PM

    by visaris (2041) on Thursday March 27 2014, @12:46PM (#22016) Journal
    "Only 80GB/s?"

    From the summary: "between the CPU and GPU".

    The connection between the EDRAM and the cores on the Xeon Phi is not CPU to GPU. The memory bandwidth available to a GPU core to/from GPU memory is much higher than 80GB/s. A better comparison would be to compare the PCIe3x16 bandwidth to nVidia's stated 80GB/s.
    Starting Score:    1  point
    Moderation   +1  
       Informative=1, Total=1
    Extra 'Informative' Modifier   0  
    Karma-Bonus Modifier   +1  

    Total Score:   3  
  • (Score: 1) by green is the enemy on Thursday March 27 2014, @05:00PM

    by green is the enemy (3805) on Thursday March 27 2014, @05:00PM (#22118)

    From the linked article:

    Knights Landing will be a standalone CPU, with an integrated six-channel DDR4-2400 memory controller, up to 16GB of on-package 3D stacked RAM, and 36 PCIe 3.0 lanes.

    This is actually exciting... Not necessarily that Intel is making a beast of a chip for supercomputers. Rather, if NVIDIA intends to compete with Intel, they will have to implement similar technology into their GPUs. This technology will then trickle down to the mass market of gaming GPUs. Massive computing power for all :)

  • (Score: 1) by Sebastopol on Friday March 28 2014, @02:50AM

    by Sebastopol (2909) on Friday March 28 2014, @02:50AM (#22364)

    Ah. Thanks for clarifying. I didn't think there was a bottleneck from CPU to GPU, but apparently there is if they are investing in higher bandwidth! (I assumed a memory controller filled local DRAM and the GPU just pointed to it, perhaps directed by instructions from the CPU, but nothing requiring that match b/w between the two.)

    • (Score: 0) by Anonymous Coward on Friday March 28 2014, @04:07AM

      by Anonymous Coward on Friday March 28 2014, @04:07AM (#22383)

      Latency is important too. The new interconnect will be much lower latency than PCIe and it is important as the GPU can seamlessly access the CPU's RAM (or another GPU's RAM) just like CPUs in a multiple socket system.
      The new Xeon Phi will have a similar interconnect. It will simply plug into a CPU socket (with Intel's QPI) rather than a PCIe slot, sharing the motherboard with Xeon EX CPUs or other Xeon Phi.