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posted by janrinok on Thursday March 27 2014, @03:03AM   Printer-friendly
from the looking-forward-to-some-pretty-pictures dept.

pbnjoe writes:

Ars technica is reporting on new devlopments in GPU interconnect tech.

From the article:

Nvidia and IBM have developed an interconnect that will be integrated into future graphics processing units, letting GPUs and CPUs share data five times faster than they can now, Nvidia announced today. The fatter pipe will let data flow between the CPU and GPU at rates higher than 80GB per second, compared to 16GB per second today. NVLink, the interconnect, will be part of the newly announced Pascal GPU architecture on track for release in 2016.

GPUs have become increasingly common in supercomputing, serving as accelerators or "co-processors" to help CPUs get work done faster. In the most recent list of the world's fastest 500 supercomputers, 53 systems used co-processors and 38 of these used Nvidia chips. The second and sixth most powerful supercomputers used Nvidia chips alongside CPUs. Intel still dominates, providing processors for 82.4 percent of Top 500 systems.

"Today's GPUs are connected to x86-based CPUs through the PCI Express (PCIe) interface, which limits the GPU's ability to access the CPU memory system and is four- to five-times slower than typical CPU memory systems," Nvidia said. "PCIe is an even greater bottleneck between the GPU and IBM Power CPUs, which have more bandwidth than x86 CPUs. As the NVLink interface will match the bandwidth of typical CPU memory systems, it will enable GPUs to access CPU memory at its full bandwidth... Although future Nvidia GPUs will continue to support PCIe, NVLink technology will be used for connecting GPUs to NVLink-enabled CPUs as well as providing high-bandwidth connections directly between multiple GPUs.

 
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  • (Score: 1) by Sebastopol on Friday March 28 2014, @02:50AM

    by Sebastopol (2909) on Friday March 28 2014, @02:50AM (#22364)

    Ah. Thanks for clarifying. I didn't think there was a bottleneck from CPU to GPU, but apparently there is if they are investing in higher bandwidth! (I assumed a memory controller filled local DRAM and the GPU just pointed to it, perhaps directed by instructions from the CPU, but nothing requiring that match b/w between the two.)

  • (Score: 0) by Anonymous Coward on Friday March 28 2014, @04:07AM

    by Anonymous Coward on Friday March 28 2014, @04:07AM (#22383)

    Latency is important too. The new interconnect will be much lower latency than PCIe and it is important as the GPU can seamlessly access the CPU's RAM (or another GPU's RAM) just like CPUs in a multiple socket system.
    The new Xeon Phi will have a similar interconnect. It will simply plug into a CPU socket (with Intel's QPI) rather than a PCIe slot, sharing the motherboard with Xeon EX CPUs or other Xeon Phi.