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posted by takyon on Wednesday September 02 2015, @11:59PM   Printer-friendly
from the month-long-news dept.

Intel's first two 14nm Skylake desktop chips, the Core i7-6700K and Core i5-6600K, were launched at Gamescom in Germany and reviewed back on Aug. 5. When the processors are set at 3 GHz, Anandtech benchmarking showed 2-3% instructions per clock (IPC) improvement over Broadwell, and over 5% IPC improvement from Haswell to Skylake. Skylake's overclocking potential seems better than both Haswell and Broadwell. One explanation is that the fully integrated voltage regulator (FIVR), which had caused heating issues in Haswell and Broadwell chips, has been removed. FIVR is expected to be reintroduced in 2017 in the generation of chips following "Kaby Lake". Skylake processors will support both DDR3L and DDR4 memory, but the performance benefits of DDR4-2133 over DDR3-1866 are minor and inconsistent.

Anandtech testing found that discrete gaming performance decreased slightly (1.3%) versus Haswell when both CPUs were limited to 3 GHz. The issue might be cleared up with firmware updates and further benchmarking, but the finding sets the tone for Skylake: Not much new for desktop users, but potentially important improvements for mobile users. Skylake on the desktop does look better when compared to older CPUs, with Skylake beating Sandy Bridge by 25-37%, and Skylake should consistently reach higher clock rates than Haswell and Broadwell.

i7-6700K/i5-6600K Review at Tom's Hardware

Following a leak of embargoed Skylake "full" lineup details, Intel pushed out its fact sheet early. Anandtech has its coverage and analysis of the full launch. You may also be interested in media improvements.

Skylake "Iris Pro Graphics 580" (GT4e) will see the introduction of a fourth "slice" of execution units (EUs), bringing the high-end from Broadwell's 48 EUs to a total of 72 EUs. However, none of the chips announced today have a fourth slice. Some of the U-series (Ultrabook) chips come with "Iris Graphics 550", with three slices and 48 EUs (GT3e). Even if a GT4e part was available, a 50% increase in EUs would not mean a 50% increase in graphics performance.

Skylake GT3 and GT4 chips will come with 64 and 128 MB of eDRAM respectively (hence GT3e and GT4e). Integrated graphics and "specific workloads" are improved by the presence of eDRAM.

Skylake chips operate across a wide range of power envelopes, from 4.5 Watts on Core M (Skylake-Y) to 91 Watts on Skylake-K. Battery life on mobile platforms will be improved, particularly when watching video due to better hardware decoding.


German IT media house Heise reports weird benchmark results [in German] for the new "Skylake" generation of Intel Core CPUs. The tested CPU exhibited more than a factor-two speedup over the previous Broadwell generation for single-thread tasks in a specific benchmark, but the performance did not scale with more cores; it even dropped below single core performance.

With somewhat stagnating clock rates in the past few years, the path to optimization has recently been to improve the Instructions-Per-Clock rate, through widening of the execution path, and, more importantly, through improved branch predition. But with major improvements in the Sandy Bridge and Broadwell generation branch predictors, Intel had reached a point of diminishing return in this area.

Do they have an unexpected ace up their sleeves, or what explains this mystery?


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  • (Score: 2) by Snotnose on Thursday September 03 2015, @12:10AM

    by Snotnose (1623) on Thursday September 03 2015, @12:10AM (#231492)

    Back in the 80's I went to a trade show and was talking to a grizzled old vet who must have been in his 40s (I was in my 20s). We were wondering if CMOS or NMOS was going to win, CMOS was the dark horse as it was so vulnerable to static electricity. One of the few things we agreed on was the process wasn't going to shrink much more than another 2-3 generations.

    14 nm. That's what, 3 atoms or something? It's farking amazing how far it's come.

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  • (Score: 3, Informative) by takyon on Thursday September 03 2015, @03:26AM

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday September 03 2015, @03:26AM (#231544) Journal

    Nah, 14nm is like 60-something atoms.

    https://en.wikipedia.org/wiki/14_nanometer [wikipedia.org]

    For comparison, the atomic radius of unstrained silicon is 111 pm (0.111 nm). Thus about 90 Si atoms would span the channel length, leading to substantial leakage.

    Ok, maybe 90 atoms. 10nm is happening, 7nm is probable (due to our IBM story [soylentnews.org]), 5nm is a maybe [wikipedia.org]. 3, 2, 1, 0.5nm could happen if designs exploit or eliminate leakage. Sounds crazy but who knows: http://www.dailytech.com/New+LeakageFree+Nanotube+Quantum+Dot+Transistor+Uses+No+Semiconductors/article31832.htm [dailytech.com]

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  • (Score: 2) by seeprime on Thursday September 03 2015, @08:49AM

    by seeprime (5580) on Thursday September 03 2015, @08:49AM (#231634)

    I think 14nm on a silicon die closer to 30 atoms wide. I'm goingn by memory on very little sleep. So, I likely am not accurate on this. I wrote a paper that mentioned quantum wires in the early 1990's. We theoretically can go down to 1 atom wide. So, until we get to under 1 nm there is room to shrink as long as the technology to do so doesn't get prohibitively expensive.