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posted by martyb on Thursday February 20 2020, @04:11PM   Printer-friendly

Scientists at Tokyo Institute of Technology (Tokyo Tech) and Socionext Inc. have designed the world's smallest all-digital phase-locked loop (PLL). PLLs are critical clocking circuits in virtually all digital applications, and reducing their size and improving their performance is a necessary step to enabling the development of next-generation technologies.

[...] The entire all-digital PLL fits in a 50 × 72 μm2 region, making it the smallest PLL to date.

A core building block of SoC devices is the phase-locked loop (PLL), a circuit that synchronizes with the frequency of a reference oscillation and outputs a signal with the same or higher frequency.

PLLs generate 'clocking signals', whose oscillations act as a metronome that provides a precise timing reference for the harmonious operation of digital devices.

[...] Manufacturers have been racing to develop increasingly smaller semiconductors. 7 nm semiconductors (a massive improvement over their 10 nm predecessor) are already in production, and methods to build 5 nm ones are now being looked at.

However, in this endeavor stands a major bottleneck. Existing PLLs require analog components, which are generally bulky and have designs that are difficult to scale down.

Scientists at Tokyo Tech and Socionext Inc., led by Prof. Kenichi Okada, have addressed this issue by implementing a 'synthesizable' fractional-N PLL, which only requires digital logic gates, and no bulky analog components, making it easy to adopt in conventional miniaturized integrated circuits.


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  • (Score: 3, Funny) by Freeman on Thursday February 20 2020, @06:27PM (5 children)

    by Freeman (732) on Thursday February 20 2020, @06:27PM (#960384) Journal

    I think I mathed that wrong, that would be a 30% improvement. Just chock it up to the marketing department.

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  • (Score: 2) by takyon on Thursday February 20 2020, @06:36PM (3 children)

    by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Thursday February 20 2020, @06:36PM (#960393) Journal

    Even minor 5-10% efficiency improvements would be massive in many industries, impacting trillions of dollars of commerce.

    But the cat is out of the bag. There is going to be a 1,000x improvement within the next decade from 3DSoC or another monolithic 3D design. Everything we're buying today is hot trash.

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    • (Score: 2) by Freeman on Thursday February 20 2020, @08:14PM (1 child)

      by Freeman (732) on Thursday February 20 2020, @08:14PM (#960425) Journal

      That's quite interesting. Seems like, so long as VR can hang in there for a while longer, viable hardware for super awesome all-in-one VR headsets is around the corner, then.

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      • (Score: 2) by takyon on Friday February 21 2020, @04:53AM

        by takyon (881) <reversethis-{gro ... s} {ta} {noykat}> on Friday February 21 2020, @04:53AM (#960588) Journal

        Depends on how you define "around the corner", but in general I agree. All of the computation will be done locally in an untethered headset (the kind of headset that typically uses Qualcomm Snapdragon chips today) and resolution + framerates will skyrocket. Up to 16K resolution over a ~200° horizontal FOV at 1000 Hz should be the end goal.

        In the case of VR you have foveated rendering and other optimizations that could reduce necessary GPU performance by over 90% [roadtovr.com]. I think this could rise to 98% for a 16K panel where only a tiny amount of the screen needs to be rendered at 16K at any given frame.

        AR will definitely see benefits with 3DSoC. One of the first things the collaboration built was a real-time imaging chip: https://youtu.be/6ir_--MgMJI?t=1198 [youtu.be]

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    • (Score: 2) by RamiK on Friday February 21 2020, @05:31AM

      by RamiK (1813) on Friday February 21 2020, @05:31AM (#960603)

      There is going to be a 1,000x improvement within the next decade from 3DSoC or another monolithic 3D design.

      Caveat emptor: MonolithIC3D were talking about a 1,000x improvement circa mid-2018 using (then) contemporary manufacturing techniques when DARPA was looking where to put their $75 million grant money.

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  • (Score: 1, Interesting) by Anonymous Coward on Thursday February 20 2020, @11:05PM

    by Anonymous Coward on Thursday February 20 2020, @11:05PM (#960484)

    They mostly deal in areas, so it is 30%^2. About 50% really, or twice as many components per square mm