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Title    Samsung Plans a "4nm" Process
Date    Sunday June 04 2017, @12:33PM
Author    martyb
Topic   
from the tiny-advances dept.
https://soylentnews.org/article.pl?sid=17/06/04/0246247

takyon writes:

Samsung has added a so-called "4nm" process to its roadmap:

At the annual Samsung Foundry Forum, Samsung announced its foundry's roadmap for the next few years, which includes an 18nm FD-SOI [(Fully Depleted – Silicon on Insulator)] generation targeting low-cost IoT chips as well as 8nm, 7nm, 6nm, 5nm, and even 4nm process generations.

[...] 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.

[...] The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.

Source.

But how many transistors per square millimeter is it?


Original Submission

Links

  1. "takyon" - https://soylentnews.org/~takyon/
  2. "added a so-called "4nm" process" - http://www.tomshardware.com/news/samsung-4nm-foundry-roadmap-revealed,34515.html
  3. "Source" - https://news.samsung.com/global/samsung-set-to-lead-the-future-of-foundry-with-comprehensive-process-roadmap-down-to-4nm
  4. "transistors per square millimeter" - https://soylentnews.org/article.pl?sid=17/03/30/1138231
  5. "Original Submission" - https://soylentnews.org/submit.pl?op=viewsub&subid=20576

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printed from SoylentNews, Samsung Plans a "4nm" Process on 2024-03-03 01:48:04