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takyon writes:

Early to embed and early to rise? Western Digital drops veil on SweRVy RISC-V based designs

Western Digital today finally flashed the results of its vow to move a billion controller cores to RISC-V designs. WD said last year it needed an open and extensible CPU architecture for its purpose-built drive controllers and other devices. As we explained then, no one knew for sure what processors WD has used for its disk and SSD controllers, though they was likely Arm-compatible chips – such as Arm9 and Cortex-M3 parts. It is known that the firm uses Intel CPUs with its ActiveScale archive systems and Tegile all-flash and hybrid arrays.

Last year, the disk and solid-state drive manufacturer vowed that RISC-V was its future, and today it announced the SweRV core, a networked cache coherency scheme, and a SweRV instruction set simulator.

[...] The SweRV core has a two-way superscalar design and is a 32-bit, nine-stage pipeline core, meaning several instructions can be loaded at once and execute simultaneously to save time. It is also an in-order core, whose relative single core performance (a simulated 4.9 CoreMark/Mhz) is expected to exceed that of many out-of-order cores, such as the Arm Cortex A15 (actual 4.72CoreMark/Mhz). Clock speeds go up to 1.8Ghz and it will be built on a 28mm [28nm] CMOS process technology.

WD said it hopes open-sourcing the core will drive development of data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more. We understand WD's ambitions for using RISC-V CPUs go beyond disk and flash drive controllers.

Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V

Related: WD Announces Client NVMe SSDs with In-House Controllers

Original Submission

1. "takyon" - https://soylentnews.org/~takyon/
2. "Early to embed and early to rise? Western Digital drops veil on SweRVy RISC-V based designs" - https://www.theregister.co.uk/2018/12/04/w_digital_swervs_into_opensource_riscv_controller_cpus/
3. "move a billion controller cores" - https://www.theregister.co.uk/2017/12/01/wdc_risc_v_edge_strategy/
4. "RISC-V" - https://www.theregister.co.uk/2018/07/10/arm_riscv_website/
5. "Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V" - https://soylentnews.org/article.pl?sid=17/11/30/0229222
6. "WD Announces Client NVMe SSDs with In-House Controllers" - https://soylentnews.org/article.pl?sid=18/03/01/1828238
7. "Original Submission" - https://soylentnews.org/submit.pl?op=viewsub&subid=30462

printed from SoylentNews, Western Digital Unveils RISC-V Controller Design on 2024-04-24 22:31:19