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DDR5 Standard to be Finalized by JEDEC in 2018

Accepted submission by takyon at 2017-04-01 11:14:44
Hardware

JEDEC [wikipedia.org] has announced [jedec.org] that it expects to finalize the DDR5 standard [arstechnica.com] by next year. It says that DDR5 will double bandwidth and density, and increase power efficiency, presumably by lowering the operating voltages again (perhaps to 1.1 V [anandtech.com]). Availability of DDR5 modules is expected by 2020:

You may have just upgraded your computer to use DDR4 recently or you may still be using DDR3, but in either case, nothing stays new forever. JEDEC, the organization in charge of defining new standards for computer memory, says that it will be demoing the next-generation DDR5 standard [jedec.org] in June of this year and finalizing the standard sometime in 2018. DDR5 promises double the memory bandwidth and density of DDR4, and JEDEC says it will also be more power-efficient, though the organization didn't release any specific numbers or targets.

The DDR4 SDRAM [wikipedia.org] specification was finalized in 2012, and DDR3 in 2007, so DDR5's arrival is to be expected (cue the Soylentils still using DDR2). One way to double the memory bandwidth of DDR5 is to double the DRAM prefetch to 16n, matching GDDR5X.

Graphics cards are beginning to ship with GDDR5X [soylentnews.org]. Some graphics cards and Knights Landing Xeon Phi chips include High Bandwidth Memory [wikipedia.org] (HBM). A third generation of HBM [arstechnica.com] will offer increased memory bandwidth, density, and more than 8 dies in a stack. Samsung has also talked about a cheaper version of HBM for consumers with a lower total bandwidth. SPARC64 XIfx chips include Hybrid Memory Cube [wikipedia.org]. GDDR6 SDRAM [wikipedia.org] could raise per-pin bandwidth to 14 Gbps, from 10-14 Gbps of GDDR5X.


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