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Samsung Plans a "4nm" Process

Accepted submission by takyon at 2017-06-03 23:22:10

Samsung has added a so-called "4nm" process [] to its roadmap:

The 4LPP process generation will be Samsung's first to use a "Gate All Around FET" (GAAFET) transistor structure, with Samsung's own implementation dubbed "Multi Bridge Channel FET" (MBCFET). The technology uses a "Nanosheet" device to overcome the physical limitations of the FinFET architecture.

Source [].

But how many transistors per square millimeter [] is it?

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