Wccftech reports [wccftech.com] that Micron plans to "introduce" NAND with 8 bits (1 byte) per cell:
Back in May of 2018, Micron introduced Quad-Level (QLC) NAND tech and, surprisingly, saw their stock tumble to pricing levels of ~$30 down from ~$60. This was the result of complex NAND pricing and supply/demand factors, not just the introduction of QLC, to be clear. I have just confirmed from multiple sources and stakeholders that Micron is intending to introduce their Octa-Level (OLC) NAND either in Q1 or latest by Q2 2019.
OLC NAND would have 28 (256) states and 28-1 (255) threshold voltages, compared to just 16 states for today's QLC NAND [theregister.co.uk].
3D QLC NAND SSDs arrived on the market in 2018. QLC NAND has lower write endurance, estimated [anandtech.com] at 1,000 program/erase (PE) cycles, compared to 3,000 P/E cycles for triple-level cell (TLC) NAND, 10,000 P/E cycles for multi-level cell (MLC) NAND, and 100,000 P/E cycles for single-level cell NAND. This exceeds previous expectations [architecting.it] of 1,000 P/E cycles for TLC NAND and 100 cycles for QLC NAND. Intel's SSD 660p drives [anandtech.com] using QLC NAND are rated for only about 0.1 drive writes per day for 5 years, or about 200 TB written on a 1 TB drive. Data retention is also reduced.
In 2013, it was reported that the U.S. Intelligence Advanced Research Projects Activity (IARPA) funded Crocus Technology development [theregister.co.uk] of 8-bits-per-cell Magnetic Logic Unit (MLU) memory, which would use two 4-bit layers:
Douglas Lee, VP for system strategy and corporate product development at Crocus, pointed out NAND and MRAM bits-per-cell limitations: "The current semiconductor non-volatile memory state-of-the-art is 3-4 bits per cell, as achieved in NAND flash memory, and is reaching the physical limits of floating gate memory technology. The current state-of-the-art in MRAM is only 1 bit per cell storage."