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takyon [soylentnews.org] writes:

Western Digital's RISC-V "SweRV" Core Design Released For Free [anandtech.com]

Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core [anandtech.com]. The SweRV core is one of several RISC-V projects the company as undertaken as part of their effort to spearhead the ISA, its ecosystem, and foster their own transition away from licensed, royalty-charging CPU cores. In accordance with the more open design goals of RISC-V, the publication of the high-level representation of SweTV means that third parties can use it in their own chip designs, which will popularize not only the particular core design, but also the RISC-V architecture in general.

The RTL design abstraction of Western Digital's RISC-V SweRV [westerndigital.com] core is now available at GitHub [github.com]. The design is licensed under the Apache 2.0 license, which is a very permissive (and non-copyleft) license that allows the core to be used free of charge, with or without modifications, and without requiring any modifications to be released in-kind. In fact the requirements of the license are quite slim; besides requiring appropriate attribution, the only other notable restriction is that third party developers cannot use Western Digital's brands to mark their work.

Previously: Western Digital to Transition Consumption of Over One Billion Cores Per Year to RISC-V [soylentnews.org]
Western Digital Unveils RISC-V Controller Design [soylentnews.org]

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