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Samsung Develops 12-Layer 3D TSV DRAM

Accepted submission by takyon at 2019-10-08 00:05:08
Hardware

Samsung has developed the first 12-layer High Bandwidth Memory stacks [anandtech.com]:

Samsung's 12-layer DRAM KGSDs (known good stack die) will feature 60,000 [through silicon via (TSV)] holes which is why the manufacturer considers its technology one of the most challenging packaging for mass production. Despite increase of the number of layers from eight to 12, thickness of the package will remain at 720 microns, so Samsung's partners will not have to change anything on their side to use the new technology. It does mean that we're seeing DRAM layers getting thinner, with acceptable yields for high-end products.

One of the first products to use Samsung's 12-layer DRAM packaging technology will be the company's 24 GB HBM2 KGSDs that will be mass produced shortly. These devices will allow developers of CPUs, GPUs, and FPGAs to install 48 GB or 96 GB of memory in case of 2048 or 4096-bit buses, respectively. It also allows for 12 GB and 6 GB stacks with less dense configurations.

"12-Hi" stacks were added to the HBM2 standard back in December [soylentnews.org], but there were no immediate plans by Samsung or SK Hynix to manufacture it.

Future AMD CPUs (particularly Epyc) may feature HBM stacks somewhere on the CPU die [wccftech.com]. Intel has already used its embedded multi-die interconnect bridge (EMIB) technology with HBM to create an advanced APU with AMD's own graphics [soylentnews.org], and is using HBM on field programmable gate arrays (FPGAs) and other products [anandtech.com].

AMD's Radeon VII GPU has 16 GB of HBM2. Nvidia's V100 GPU has 16 or 32 GB on a 4,096-bit memory bus.

Also at Electronics Weekly [electronicsweekly.com].


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