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Samsung "X-Cube" Stacks SRAM Dies on Top of Logic Die

Accepted submission by takyon at 2020-08-14 11:34:06

Samsung Announces "X-Cube" 3D TSV SRAM-Logic Die Stacking Technology []

Yesterday, Samsung Electronics had announced a new 3D IC packaging technology called eXtended-Cube, or "X-Cube", allowing chip-stacking of SRAM dies on top of a base logic die through TSVs.

Current TSV deployments in the industry mostly come in the form of stacking memory dies on top of a memory controller die in high-bandwidth-memory (HBM) modules that are then integrated with more complex packaging technologies, such as silicon interposers, which we see in today's high-end GPUs and FPGAs, or through other complex packaging such as Intel's EMIB [].

Samsung's X-Cube is quite different to these existing technologies in that it does away with intermediary interposers or silicon bridges, and directly connects a stacked chip on top of the primary logic die of a design.

Samsung has built a 7nm EUV test chip using this methodology by integrating an SRAM die on top of a logic die. The logic die is designed with TSV pillars which then connect to µ-bumps with only 30µm pitch, allowing the SRAM-die to be directly connected to the main die without intermediary mediums. The company this is the industry's first such design with an advanced process node technology.

[...] Stacking more valuable SRAM instead of DRAM on top of the logic chip would likely represent a higher value proposition and return-on-investment to chip designers, as this would allow smaller die footprints for the base logic dies, with larger SRAM cache structures being able to reside on the stacked die. Such a large SRAM die would naturally also allow for significantly more SRAM that would allow for higher performance and lower power usage for a chip.

3D SRAM [] is not a new idea, but this kind of stacking could become commonplace in CPUs within a few years. SRAM takes up a large amount of CPU die area, so stacking it into layers above or near cores could be beneficial.

Also at The Register [] and Guru3D [].

Related: Intel Details Lakefield CPU SoC With 3D Packaging and Big/Small Core Configuration []
AMD Plans to Stack DRAM and SRAM on Top of its Future Processors []

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