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takyon [soylentnews.org] writes:

European Processor Initiative Receives First EPAC RISC-V Sample Chips for Testing [tomshardware.com]

European Processor Initiative (EPI) has been working on providing independence for the European Union in the high-performance computing (HPC) field, by developing custom RISC-V-based accelerators. Called the European Processor Accelerator (EPAC) chip, designed for high efficiency and high throughput computation, it has been successfully taped out and is being tested at EPI's labs [european-processor-initiative.eu].

[...] [Today], the project has delivered its promises as the very first batch of chips are being tested in EPI's labs. The RISC-V processors are designs containing multiple special-purpose accelerators, all centered around the RISC-V ISA and its design principles. The processor contains four tiles of Vector Processing Units (VPUs) made up from Avispado RISC-V core designed by SemiDynamics, and vector processing elements design by Barcelona Supercomputing Center and the University of Zagreb. In each tile, there are home nodes and L2 cache for cache systems, which are the contributions of Chalmers and FORTH. For additional acceleration, there are Stencil and Tensor accelerators (STX) engineered by Fraunhofer IIS, ITWM, and ETH Zürich, and the variable precision processor (VRP) deigned by CEA LIST.

Also at The Register [theregister.com].

Related: U.S.-Based Chip-Tech Group Moving to Switzerland Over Trade Curb Fears [soylentnews.org]

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