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takyon [soylentnews.org] writes:

Imec Presents Sub-1nm Process and Transistor Roadmap Until 2036: From Nanometers to the Angstrom Era [tomshardware.com]

Imec, the most advanced semiconductor research firm in the world, recently shared its sub-'1nm' silicon and transistor roadmap at its Future Summit event in Antwerp, Belgium. The roadmap gives us a rough idea of the timelines through 2036 for the next major process nodes and transistor architectures the company will research and develop in its labs in cooperation with industry giants, like TSMC, Intel, Samsung, and ASML, among many others.

The roadmap includes breakthrough transistor designs that evolve from the standard FinFET transistors that will last until 3nm, to new Gate All Around (GAA) nanosheets and forksheet designs at 2nm and A7 (seven angstroms), respectively, followed by breakthrough designs like CFETs and atomic channels at A5 and A2. As a reminder, ten Angstroms are equal to 1nm, so Imec's roadmap encompasses sub-'1nm' process nodes.

TSMC to Initiate 1.4nm Process Technology R&D [tomshardware.com]

At processor manufacturers, fundamental and applied research and development work never stops, so now that Taiwan Semiconductor Manufacturing Co. has outlined a timeline for its N2 (2 nm-class) fabrication process [tomshardware.com] that will enter high-volume manufacturing (HVM) in 2025, it is time for the company to start thinking about a succeeding node. If a new rumor is to be believed, TSMC is set to formally announce its 1.4 nm-class technology in June.

TSMC plans to reassign the team that developed its N3 (3 nm-class) node to development of its 1.4 nm-class fabrication process in June, reports Business Korea [businesskorea.co.kr]. Typically, foundries and chip designers never formally announce R&D milestones, so we are unlikely going to see a TSMC press release saying that development of its 1.4 nm technology had been started. Meanwhile, TSMC is set to host its Technology Symposium in mid-June [tsmc.com] and there the company may outline some brief details about the node that will succeed its N2 manufacturing process.

N2 will be TSMC's [wikipedia.org] first node to use gate-all-around field-effect transistors [wikipedia.org] (GAAFETs). Subsequent nodes may use high-numerical aperture [semiengineering.com] (high-NA) extreme ultraviolet (EUV) lithography instead of regular EUV.

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