from the what-90-quadrillion-rabbit's-ears-look-like dept.
The Register's new sister site, The Platform, broke news of an upcoming 180 petaflops supercomputer named "Aurora" to be installed at the Argonne National Laboratory. The system will reportedly use 2.7x the power (from 4.8 megawatts to 13 megawatts) to deliver 18x the peak performance of Argonne's existing Mira supercomputer (more detail here).
Aurora will use Intel's upcoming 10nm "Knights Hill" Xeon Phi processors and a second-generation Omni-Path optical interconnect with far greater bandwidth than current designs. The storage capacity will exceed 150 petabytes. Cray Inc. will manufacture the system, which will cost $200 million and round out the CORAL trio of supercomputers, including the 150-300 PFLOPS Summit at Oak Ridge National Laboratory and the 100+ PFLOPS Sierra at Lawrence Livermore National Laboratory. The other two systems will use IBM Power9 and NVIDIA Volta chips.
An 8.5 petaflops, 1.7 MW secondary system named Theta will be built in 2016.
According to Intel and Argonne National Laboratory:
Research goals for the Aurora system include: more powerful, efficient and durable batteries and solar panels; improved biofuels and more effective disease control; improving transportation systems and enabling production of more highly efficient and quieter engines; and wind turbine design and placement for improved efficiency and reduced noise.
Editor's Note: For the purists, and from a maintainer of the TOP500 list, What is a Mflop/s?:
Mflop/s is a rate of execution, millions of floating point operations per second. Whenever this term is used it will refer to 64 bit floating point operations and the operations will be either addition or multiplication. Gflop/s refers to billions of floating point operations per second and Tflop/s refers to trillions of floating point operations per second.
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The TOP500 List of the world's fastest supercomputers for June 2015 has been released. China's Tianhe-2 remains the leader with 33.86 petaflops on the LINPACK benchmark. It has topped the list since June 2013. The only new supercomputer in the top 10 is the Shaheen II in Saudi Arabia, a 5.536 PFlop/s Cray XC40 system using 196,608 Intel Xeon E5-2698v3 cores.
The Platform has an analysis of the results. Although performance growth is slowing, pre-exascale supercomputers (100+ petaflops) can be expected within the next two to three years. The U.S. Department of Energy's Aurora supercomputer will deliver 180 petaflops of performance in 2018. Around the same time, the Summit supercomputer is expected to reach 150-300 petaflops while Sierra will reach 100+ petaflops. ~1 exaflop supercomputers are expected to appear around 2018-2022.
The June 2015 Green500 list ranking supercomputers by megaflops per watt will be available sometime later in the month. Here is the November 2014 Green500 list. The Piz Daint supercomputer appears within the top 10 on both lists.
The Platform reports on IBM's updated POWER CPU roadmap. Next year's POWER8+ will add Nvidia's NVLink interconnect to boost bandwidth. POWER9 will move down to a 14nm process node around 2017, and POWER10 will move to 10nm around 2020. A 7nm POWER chip would likely appear around 2023 at the earliest:
The interesting thing about these roadmaps is that the Power8+ processor will come out next year and will have NVLink high-bandwidth interconnects just like the forthcoming "Pascal" GP100 Tesla coprocessor from Nvidia. With NVLink, Nvidia is putting up to four 20 GB/sec ports onto the GPU coprocessor to speed up data transfers between the high bandwidth memory on the GPU cards and to improve the performance of virtual addressing across those devices. With the addition of NVLink ports on the Power8+ processor, those creating hybrid systems will be able to implement virtual memory between the CPU and GPU in an NVLink cluster without having to resort to IBM's Coherent Accelerator Processor Interface (CAPI), which debuted with the Power8 chip last year and which offers similar coherence across a modified PCI-Express link.
[...] We think that IBM could be adding some form of high bandwidth memory to the Power9 chip package, particularly variants aimed at HPC and hyperscale workloads that are not intended for multi-processor systems. But IBM has said nothing about its plans to adopt 3D stacked memory on its processors thus far, even though it has done plenty of fundamental research in this area. We also wonder if IBM will use the process shrink to lower the power consumption of the Power9 chips and perhaps even simplify the cores now that it has officially designated GPUs and FPGAs are coprocessors for the Power line. (Why add vector units if you want to offload to GPUs and FPGAs?)
What is new and interesting on the above roadmap is confirmation that IBM is working on a Power10 processor, which is slated for around 2020 or so and which will be based on the 10 nanometer processes under development at Globalfoundries. With the Power10, as with the Power7, Power8, and Power9 before it, IBM is changing the chip microarchitecture and chip manufacturing process at the same time. This IBM roadmap above does not show a Power9+ or Power10+ kicker, but both could come to pass if the market demands some tweaks to the microarchitecture around half-way between those three-year gaps between Power generations.
IBM's POWER9 chips and Nvidia's Volta GPUs will be featured in Summit and Sierra, two upcoming U.S. Department of Energy supercomputers that will reach 100-300 petaflops.
The upcoming Aurora supercomputer at the Argonne National Laboratory is estimated to have 180 petaflops of peak performance. Here are some of the early science projects that will be run on it (descriptions at source):
- Extending Moore's Law computing with quantum Monte Carlo
- Design and evaluation of high-efficiency boilers for energy production using a hierarchical V/UQ approach
- High-fidelity simulation of fusion reactor boundary plasmas
- NWChemEx: Tackling chemical, materials and biochemical challenges in the exascale era
- Extreme-scale cosmological hydrodynamics
- Extreme-scale unstructured adaptive [computational fluid dynamics]
- Benchmark simulations of shock-variable density turbulence and shock-boundary layer interactions with applications to engineering modeling
- Lattice quantum chromodynamics calculations for particle and nuclear physics
- Metascalable layered materials genome
- Free energy landscapes of membrane transport proteins
An article at Argonne National Laboratory describes four co-design centers working towards "exascale" supercomputing:
As collaborators in four co-design centers created by the U.S. Department of Energy's (DOE) Exascale Computing Project (ECP), researchers at the DOE's Argonne National Laboratory are helping to solve some of these complex challenges and pave the way for the creation of exascale supercomputers.
The term 'co-design' describes the integrated development and evolution of hardware technologies, computational applications and associated software. In pursuit of ECP's mission to help people solve realistic application problems through exascale computing, each co-design center targets different features and challenges relating to exascale computing.
- Co-design Center for Online Data Analysis and Reduction at the Exascale (CODAR)
- Center for Efficient Exascale Discretizations (CEED)
- Co-design Center for Particle Applications (CoPA)
- Block-Structured AMR Co-design Center
(Score: 0) by Anonymous Coward on Friday April 10 2015, @11:47AM
Can't wait to see Skylake land on the desktop and watch it struggle with a perfectly ordinary mixture of SSE and AVX code. Who knows, maybe AVX-512 will be an actual improvement. But for now I'm still compiling for AVX-128 even on Haswell because AVX-256 is a flop.
(Score: 2) by takyon on Friday April 10 2015, @11:57AM
Intel rekt you yet again:
http://wccftech.com/mainstream-intel-core-processors-support-avx-512-skylake-xeon/ [wccftech.com]
http://www.kitguru.net/components/cpu/anton-shilov/intel-skylake-processors-for-pcs-will-not-support-avx-512-instructions/ [kitguru.net]
Cannonlake = formerly Skymont = 10nm "tick"
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 0) by Anonymous Coward on Friday April 10 2015, @12:13PM
Pretty sure a Xeon fits on a desk, so yeah. Skylake, desktop.
(Score: 2) by takyon on Friday April 10 2015, @12:18PM
Hey, it's your money. We can call Xeon a desktop chip.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 0) by Anonymous Coward on Friday April 10 2015, @12:23PM
Dell sells Xeon as a desktop chip, therefore it is a desktop chip.
(Score: 4, Touché) by tibman on Friday April 10 2015, @05:56PM
I have linux on my desktop. This must be the year of linux on the desktop : )
SN won't survive on lurkers alone. Write comments.
(Score: 2) by fadrian on Friday April 10 2015, @12:44PM
Why do all these articles have a bunch of crap in them about what the research project are going to do? Sure they'll do all that kind of stuff on it, but why don't they just be honest? It's going to crunch lots and lots of numbers and I really don't care, as a computer guy, what those numbers say - I just care that they show up in memory after the operation completes. That's the cool part. And that's cool enough.
That is all.
(Score: 0) by Anonymous Coward on Friday April 10 2015, @12:48PM
You forgot the most important step where it emails you the results so you can print a report to give to your pointy haired boss.
(Score: 3, Insightful) by takyon on Friday April 10 2015, @12:54PM
Damned if I do, damned if I don't.
[SIG] 10/28/2017: Soylent Upgrade v14 [soylentnews.org]
(Score: 0) by Anonymous Coward on Friday April 10 2015, @12:59PM
So you don't care about highly efficient quiet engines for drones that sneak up on muslims and explode their fucking asses? You dirty terrorist sympathizer.
(Score: 2) by fadrian on Friday April 10 2015, @05:12PM
Yes, the world is a crappy place. As such, we should try to make it less crappy. However, we should, as a general principal, do our best to not make it crappier in the process of making it a less crappy place. In addition, we should also attempt to minimize the crap we must spew in the process.
Because that's what war is - crap. It might be necessary as crap, too, at least until we all evolve socially a bit more, but it doesn't mean we all have to become German with respect to the whole thing, if you catch my drift. But what do I know - I'm simply a humble, loveable engineer...
That is all.
(Score: 1, Interesting) by Anonymous Coward on Friday April 10 2015, @08:00PM
I've recently been hired into this team, and you better believe my first damn question in the interview was whether this thing will be used for science or used for weapons/spying/other abuses.
(Score: 2, Interesting) by Anonymous Coward on Friday April 10 2015, @04:50PM
US nuclear fears block Intel China supercomputer update - http://www.bbc.com/news/technology-32247532 [bbc.com]
The US Aurora computer is trying to take the TOP500 top rating away from the Chinese Tianhe-2 (or followon).
Intel takes the export restriction in the shorts, oh wait, saved by a new contract with the US.
All for some sort of penis size thing between US and China.
Unless, of course, you think China is out to get us, unable to make their own supercomputers, or lacks the will (note: Taiwan has several 20 nm fabs and China has been looking for a reason to take that rebel base over).
Or, admit that China has more people (greatly), land mass (slightly), are hording all the "rare earths"(snort) and willingness to be a first world power, and try to play nice with them.
(naw, never going to happen; they have a great firewall, a great cannon,
and once ran over a protestor with a tank http://en.wikipedia.org/wiki/Jackson_State_killings [wikipedia.org] - oops, linked to wrong countries killing, sorry. At least I picked the second worst killing in that month.).
We are all boned.